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- interface change to rams

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
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lib/misc/ram_wb.vhd
+31 -25
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@@ -30,15 +30,17 @@ END ram_wb;
ARCHITECTURE behavior OF ram_wb IS
constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
signal data_en : std_logic;
signal ram_en : std_logic;
signal we : unsigned(3 downto 0);
signal re : std_logic;
begin
we <= SEL_I and (3 downto 0 => WE_I);
SRDY_O <= CYC_I;
data_en <= CYC_I and STB_I and MRDY_I;
SRDY_O <= CYC_I;
ram_en <= CYC_I and STB_I and MRDY_I;
we <= SEL_I and (3 downto 0 => ram_en and WE_I);
re <= ram_en and not WE_I;
data_valid_register:
process(CLK_I)
@@ -47,7 +49,7 @@ data_valid_register:
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= data_en and not WE_I;
ACK_O <= re;
end if;
end if;
end process;
@@ -61,11 +63,12 @@ inst_ram_0 : entity work.dpram_1w1r1c_ra
PORT MAP
(
clk => CLK_I,
en => data_en,
we => we(0),
addr => ADDR_I(addr_width+1 downto 2),
din => DAT_I(7 downto 0),
dout => DAT_O(7 downto 0)
we_a => we(0),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(7 downto 0),
dout_b => DAT_O(7 downto 0)
);
inst_ram_1 : entity work.dpram_1w1r1c_ra
@@ -77,11 +80,12 @@ inst_ram_1 : entity work.dpram_1w1r1c_ra
PORT MAP
(
clk => CLK_I,
en => data_en,
we => we(1),
addr => ADDR_I(addr_width+1 downto 2),
din => DAT_I(15 downto 8),
dout => DAT_O(15 downto 8)
we_a => we(1),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(15 downto 8),
dout_b => DAT_O(15 downto 8)
);
inst_ram_2 : entity work.dpram_1w1r1c_ra
@@ -93,11 +97,12 @@ inst_ram_2 : entity work.dpram_1w1r1c_ra
PORT MAP
(
clk => CLK_I,
en => data_en,
we => we(2),
addr => ADDR_I(addr_width+1 downto 2),
din => DAT_I(23 downto 16),
dout => DAT_O(23 downto 16)
we_a => we(2),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(23 downto 16),
dout_b => DAT_O(23 downto 16)
);
inst_ram_3 : entity work.dpram_1w1r1c_ra
@@ -109,11 +114,12 @@ inst_ram_3 : entity work.dpram_1w1r1c_ra
PORT MAP
(
clk => CLK_I,
en => data_en,
we => we(3),
addr => ADDR_I(addr_width+1 downto 2),
din => DAT_I(31 downto 24),
dout => DAT_O(31 downto 24)
we_a => we(3),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(31 downto 24),
dout_b => DAT_O(31 downto 24)
);