jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- interface change to rams

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_dcache.vhd
+6 -6
View File
@@ -69,8 +69,8 @@ COMPONENT dpram_2w2r2c_ra is
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
@@ -268,8 +268,8 @@ inst_tag_ram : dpram_2w2r2c_ra
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => '1',
re_a => '1',
re_b => '1',
we_a => tag_ram_we,
we_b => '0',
addr_a => tag_ram_addr_wr,
@@ -294,8 +294,8 @@ gen_data_ram:
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => '1',
re_a => '1',
re_b => '1',
we_a => cpu_data_ram_we(i),
we_b => ctrl_data_ram_we(i),
addr_a => ctrl_data_ram_addr,
lib/CPUs/MIPS/src/core/mips_icache.vhd
+8 -10
View File
@@ -64,9 +64,8 @@ COMPONENT dpram_1w1r2c_ra
PORT (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
re_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
@@ -84,8 +83,8 @@ COMPONENT dpram_2w2r2c_ra is
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
@@ -271,10 +270,10 @@ inst_tag_ram : dpram_2w2r2c_ra
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => tag_ram_re,
we_a => tag_ram_we,
we_b => '0',
re_a => '1',
we_a => tag_ram_we,
re_b => tag_ram_re,
we_b => '0',
addr_a => tag_ram_addr_wr,
addr_b => tag_ram_addr_rd,
din_a => tag_ram_data_wr,
@@ -293,8 +292,7 @@ inst_data_ram : dpram_1w1r2c_ra
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => data_ram_we,
en_b => data_ram_re,
re_b => data_ram_re,
we_a => data_ram_we,
addr_a => data_ram_addr_wr,
addr_b => data_ram_addr_rd,