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- JBus-ports are unsigned instead of word_t

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git-svn-id: http://moon:8086/svn/vhdl/trunk@283 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-24 14:54:08 +00:00
parent a691c0b7fa
commit 2151b77ef3
1 changed files with 4 additions and 4 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+4 -4
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@@ -48,9 +48,9 @@ ARCHITECTURE behavior OF tb_mips_top IS
signal clk : STD_LOGIC := '0';
signal ACK_I : STD_LOGIC := '0';
signal SRDY_I : STD_LOGIC := '0';
signal ADDR_O : word_t;
signal DAT_I : word_t := (others => '0');
signal DAT_O : word_t;
signal ADDR_O : unsigned(31 downto 0);
signal DAT_I : unsigned(31 downto 0) := (others => '0');
signal DAT_O : unsigned(31 downto 0);
signal WE_O : STD_LOGIC;
signal SEL_O : unsigned(3 downto 0);
signal CYC_O : STD_LOGIC;
@@ -106,7 +106,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
signal mem_area : mem_area_t;
type word_array_t is array (natural range <>) of word_t;
type word_array_t is array (natural range <>) of unsigned(31 downto 0);
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);