diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index 60fb374..6a95b4b 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -48,9 +48,9 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	signal clk			: STD_LOGIC := '0';
 	signal ACK_I		: STD_LOGIC := '0';
 	signal SRDY_I		: STD_LOGIC := '0';
-	signal ADDR_O		: word_t;
-	signal DAT_I		: word_t := (others => '0');
-	signal DAT_O		: word_t;
+	signal ADDR_O		: unsigned(31 downto 0);
+	signal DAT_I		: unsigned(31 downto 0) := (others => '0');
+	signal DAT_O		: unsigned(31 downto 0);
 	signal WE_O			: STD_LOGIC;
 	signal SEL_O		: unsigned(3 downto 0);
 	signal CYC_O		: STD_LOGIC;
@@ -106,7 +106,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
 	signal mem_area : mem_area_t;
 
-	type word_array_t is array (natural range <>) of word_t;
+	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
 	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
 	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);