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- Added Sync. SRAM

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git-svn-id: http://moon:8086/svn/vhdl/trunk@75 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-19 20:02:45 +00:00
parent 8a8adce98e
commit 20b3bfb41b
2 changed files with 255 additions and 91 deletions
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projects/mips_sys/src/tb_mips_sys.vhd
+105 -59
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@@ -83,13 +83,25 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal sys_usb_rstn : std_logic;
signal sys_usb_int : std_logic := '0';
signal sys_flash_d : word_t;
signal sys_flash_a : unsigned(24 downto 0);
signal sys_flash_ssram_d : word_t;
signal sys_flash_ssram_a : unsigned(24 downto 0);
signal sys_flash_ssram_we_n : std_logic;
signal sys_flash_ssram_oe_n : std_logic;
signal sys_flash_ce : std_logic;
signal sys_flash_wrn : std_logic;
signal sys_flash_rdn : std_logic;
signal sys_flash_rstn : std_logic;
signal sys_flash_byten : std_logic;
signal sys_ssram_clk_fb : std_logic;
signal sys_ssram_clk : std_logic;
signal sys_ssram_cke_n : std_logic;
signal sys_ssram_ce_n : std_logic;
signal sys_ssram_bw_n : unsigned(3 downto 0);
signal sys_ssram_dp : unsigned(3 downto 0);
signal sys_ssram_adv : std_logic;
signal sys_ssram_mode : std_logic;
signal sys_ssram_zz : std_logic;
signal flash_reg : word_t;
type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
@@ -105,60 +117,92 @@ uut: entity work.mips_sys
-- )
PORT MAP
(
sys_rst_n_in => sys_rst_n_in,
sys_clk_in => sys_clk_in,
sys_btn => btn,
sys_dip => dip,
sys_led => led,
sys_rst_n_in => sys_rst_n_in,
sys_clk_in => sys_clk_in,
sys_btn => btn,
sys_dip => dip,
sys_led => led,
sys_rx => sys_rx,
sys_tx => sys_tx,
sys_rx => sys_rx,
sys_tx => sys_tx,
sys_lcd_d => sys_lcd_d,
sys_lcd_e => sys_lcd_e,
sys_lcd_rs => sys_lcd_rs,
sys_lcd_rw => sys_lcd_rw,
sys_lcd_d => sys_lcd_d,
sys_lcd_e => sys_lcd_e,
sys_lcd_rs => sys_lcd_rs,
sys_lcd_rw => sys_lcd_rw,
sys_user_rom_addr => sys_user_rom_addr,
sys_user_rom_din => sys_user_rom_din,
sys_user_rom_en => sys_user_rom_en,
sys_user_rom_clk => sys_user_rom_clk,
sys_user_rom_addr => sys_user_rom_addr,
sys_user_rom_din => sys_user_rom_din,
sys_user_rom_en => sys_user_rom_en,
sys_user_rom_clk => sys_user_rom_clk,
sys_sdr_clk_p => sys_sdr_clk_p,
sys_sdr_clk_n => sys_sdr_clk_n,
sys_sdr_cke_q => sys_sdr_cke_q,
sys_sdr_clk_fb => sys_sdr_clk_fb,
sys_sdr_cs_qn => sys_sdr_cs_qn,
sys_sdr_ras_qn => sys_sdr_ras_qn,
sys_sdr_cas_qn => sys_sdr_cas_qn,
sys_sdr_we_qn => sys_sdr_we_qn,
sys_sdr_dm_q => sys_sdr_dm_q,
sys_sdr_dqs_q => sys_sdr_dqs_q,
sys_sdr_ba_q => sys_sdr_ba_q,
sys_sdr_a_q => sys_sdr_a_q,
sys_sdr_data => sys_sdr_data,
sys_sdr_clk_p => sys_sdr_clk_p,
sys_sdr_clk_n => sys_sdr_clk_n,
sys_sdr_cke_q => sys_sdr_cke_q,
sys_sdr_clk_fb => sys_sdr_clk_fb,
sys_sdr_cs_qn => sys_sdr_cs_qn,
sys_sdr_ras_qn => sys_sdr_ras_qn,
sys_sdr_cas_qn => sys_sdr_cas_qn,
sys_sdr_we_qn => sys_sdr_we_qn,
sys_sdr_dm_q => sys_sdr_dm_q,
sys_sdr_dqs_q => sys_sdr_dqs_q,
sys_sdr_ba_q => sys_sdr_ba_q,
sys_sdr_a_q => sys_sdr_a_q,
sys_sdr_data => sys_sdr_data,
sys_usb_d => sys_usb_d,
sys_usb_a => sys_usb_a,
sys_usb_csn => sys_usb_csn,
sys_usb_wrn => sys_usb_wrn,
sys_usb_rdn => sys_usb_rdn,
sys_usb_rstn => sys_usb_rstn,
sys_usb_int => sys_usb_int,
sys_usb_d => sys_usb_d,
sys_usb_a => sys_usb_a,
sys_usb_csn => sys_usb_csn,
sys_usb_wrn => sys_usb_wrn,
sys_usb_rdn => sys_usb_rdn,
sys_usb_rstn => sys_usb_rstn,
sys_usb_int => sys_usb_int,
sys_flash_d => sys_flash_d,
sys_flash_a => sys_flash_a,
sys_flash_ce => sys_flash_ce,
sys_flash_wrn => sys_flash_wrn,
sys_flash_rdn => sys_flash_rdn,
sys_flash_rstn => sys_flash_rstn,
sys_flash_byten => sys_flash_byten,
sys_flash_ssram_d => sys_flash_ssram_d,
sys_flash_ssram_a => sys_flash_ssram_a,
sys_flash_ssram_we_n => sys_flash_ssram_we_n,
sys_flash_ssram_oe_n => sys_flash_ssram_oe_n,
sys_flash_ce => sys_flash_ce,
sys_flash_rstn => sys_flash_rstn,
sys_flash_byten => sys_flash_byten,
sys_error => sys_error
sys_ssram_clk_fb => sys_ssram_clk_fb,
sys_ssram_clk => sys_ssram_clk,
sys_ssram_cke_n => sys_ssram_cke_n,
sys_ssram_ce_n => sys_ssram_ce_n,
sys_ssram_bw_n => sys_ssram_bw_n,
sys_ssram_dp => sys_ssram_dp,
sys_ssram_adv => sys_ssram_adv,
sys_ssram_mode => sys_ssram_mode,
sys_ssram_zz => sys_ssram_zz,
sys_error => sys_error
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
inst_ssram : entity work.cy7c1354
PORT MAP
(
Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O
Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O
Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address
Mode => sys_ssram_mode, -- Burst Mode
Clk => sys_ssram_clk, -- Clk
CEN_n => sys_ssram_cke_n, -- CEN#
AdvLd_n => sys_ssram_adv, -- Adv/Ld#
Bwa_n => sys_ssram_bw_n(0), -- Bwa#
Bwb_n => sys_ssram_bw_n(1), -- BWb#
Bwc_n => sys_ssram_bw_n(2), -- Bwc#
Bwd_n => sys_ssram_bw_n(3), -- BWd#
Rw_n => sys_flash_ssram_we_n, -- RW#
Oe_n => sys_flash_ssram_oe_n, -- OE#
Ce1_n => sys_ssram_ce_n, -- CE1#
Ce2 => '1', -- CE2
Ce3_n => '0', -- CE3#
Zz => sys_ssram_zz
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
port map (
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
@@ -174,8 +218,8 @@ uut: entity work.mips_sys
dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16
port map (
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
@@ -191,7 +235,9 @@ uut: entity work.mips_sys
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
);
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
sys_ssram_clk_fb <= sys_ssram_clk after 4 ns;
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
@@ -222,18 +268,18 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
end if;
end process;
FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
begin
if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
flash_reg <= sys_flash_d;
if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
flash_reg <= sys_flash_ssram_d;
end if;
end process;
FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
FLASH_READ: process(sys_flash_ce, sys_flash_ssram_oe_n, flash_reg)
begin
sys_flash_d <= (others => 'Z') after 10 ns;
if sys_flash_rdn = '0' and sys_flash_ce = '1' then
sys_flash_d <= flash_reg after 10 ns;
sys_flash_ssram_d <= (others => 'Z') after 10 ns;
if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
sys_flash_ssram_d <= flash_reg after 10 ns;
end if;
end process;