diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
index 2090a07..b72f12d 100644
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ b/projects/mips_sys/src/mips_sys_sim.vhd
@@ -105,14 +105,25 @@ PORT
 	sys_usb_rstn		: out std_logic;
 	sys_usb_int			: in std_logic;
 
-	sys_flash_d			: inout unsigned(31 downto 0);
-	sys_flash_a			: out unsigned(24 downto 0);
-	sys_flash_ce		: out std_logic;
-	sys_flash_wrn		: out std_logic;
-	sys_flash_rdn		: out std_logic;
-	sys_flash_rstn		: out std_logic;
-	sys_flash_byten		: out std_logic;	
-	sys_error			: out unsigned(1 downto 0) -- indicates Errors
+	sys_flash_ssram_d		: inout unsigned(31 downto 0);
+	sys_flash_ssram_a		: out unsigned(24 downto 0);
+	sys_flash_ce			: out std_logic;
+	sys_flash_ssram_we_n	: out std_logic;
+	sys_flash_ssram_oe_n	: out std_logic;
+	sys_flash_rstn			: out std_logic;
+	sys_flash_byten			: out std_logic;	
+	
+	sys_ssram_clk			: out std_logic;
+	sys_ssram_clk_fb		: in std_logic;
+	sys_ssram_cke_n			: out std_logic;
+	sys_ssram_ce_n			: out std_logic;
+	sys_ssram_bw_n			: out unsigned(3 downto 0);
+	sys_ssram_dp			: inout unsigned(3 downto 0);
+	sys_ssram_adv			: out std_logic;
+	sys_ssram_mode			: out std_logic;
+	sys_ssram_zz			: out std_logic;
+	
+	sys_error				: out unsigned(1 downto 0) -- indicates Errors
 	
 );
 --	attribute BUFFER_TYPE : string;
@@ -324,14 +335,24 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal rst_in		: std_logic;
 	signal int_uart_rx	: std_logic;
 	signal locked		: std_logic;
-	signal usb_addr 	: unsigned(31 downto 0);
-	signal flash_addr	: unsigned(31 downto 0);
-
+	signal ADDR_I_usb 	: unsigned(31 downto 0);
+	signal ADDR_I_flash	: unsigned(31 downto 0);
+	signal ADDR_I_ssram	: unsigned(31 downto 0);
+	signal flash_a		: unsigned(24 downto 0);
+	signal ssram_a		: unsigned(24 downto 0);
+	signal ssram_clk	: std_logic;
+	signal ssram_oe_n	: std_logic;
+	signal ssram_we_n	: std_logic;
+	signal flash_oe_n	: std_logic;
+	signal flash_we_n	: std_logic;
+	signal dcm_locked	: std_logic;
+	signal dcm_clk0		: std_logic;
+	
 	-- Arbiter
 	constant ARB_MAX_MASTER	: natural := 2;
-	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
-	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
 	
 	-- J-Bus signals
 	signal INT	 		: unsigned(5 downto 0);
@@ -414,6 +435,11 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal SRDY_O_vga	: std_logic;
 	signal SDAT_O_vga	: unsigned(31 downto 0);
 
+	signal CYC_I_ssram	: std_logic;
+	signal ACK_O_ssram	: std_logic;
+	signal SRDY_O_ssram	: std_logic;
+	signal SDAT_O_ssram	: unsigned(31 downto 0);
+
 	signal gpo0			: unsigned(31 downto 0);
 	signal gpo1			: unsigned(31 downto 0);
 	signal gpi0			: unsigned(31 downto 0);
@@ -422,7 +448,7 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal debug		: unsigned(1 downto 0);
 
 	-- DDR SDRAM
-	constant BURST_LEN		: natural := 2;
+	constant BURST_LEN	: natural := 2;
 
 	
 --	attribute rom_style: string;
@@ -430,7 +456,7 @@ ARCHITECTURE behavior OF mips_sys IS
 --	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
 --	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
 
-	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
+	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
 	signal mem_area : mem_area_t;
 
 BEGIN
@@ -443,10 +469,15 @@ BEGIN
 	rst					<= not locked;
 	sys_usb_rstn		<= not gpo1(0);
 	sys_flash_byten		<= '1';
-	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
-	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
-
+	ADDR_I_usb			<= X"0000000" & "00" & ADDR_O(3 downto 2);
+	ADDR_I_flash		<= "0000000" & ADDR_O(25 downto 2) & '0';
+	ADDR_I_ssram		<= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
 
+	sys_flash_ssram_a		<= flash_a when CYC_I_flash = '1' else ssram_a;
+	sys_flash_ssram_we_n	<= ssram_we_n and flash_we_n;
+	sys_flash_ssram_oe_n	<= ssram_oe_n and flash_oe_n;
+	sys_ssram_clk			<= clk;
+	
 	---------------------------------------------------------------
 	-- Arbiter
 	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
@@ -514,7 +545,8 @@ mem_mux:
 		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
 			mem_area	<= mem_rom;
 		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-			mem_area	<= mem_ram;
+			mem_area	<= mem_ssram;
+--			mem_area	<= mem_ram;
 		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
 			mem_area	<= mem_sdram;
 		end if;
@@ -533,6 +565,7 @@ signal_mux:
 		CYC_I_ram		<= '0';
 		CYC_I_sdram		<= '0';
 		CYC_I_vga		<= '0';
+		CYC_I_ssram		<= '0';
 		
 		case mem_area is
 
@@ -563,6 +596,9 @@ signal_mux:
 		when mem_vga =>
 			CYC_I_vga		<= CYC_O;
 
+		when mem_ssram =>
+			CYC_I_ssram		<= CYC_O;
+
 		when others => null;
 		
 		end case;
@@ -584,9 +620,10 @@ urom_ack_register:
 	end process;
 	
 ------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
- 	MDAT_I		<=	SDAT_O_sdram when CYC_I_sdram = '1' else
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
+ 	MDAT_I		<=	SDAT_O_ssram when CYC_I_ssram = '1' else
+ 					SDAT_O_sdram when CYC_I_sdram = '1' else
 					SDAT_O_ram when CYC_I_ram = '1' else
 					SDAT_O_rom when CYC_I_rom = '1' else
 					SDAT_O_urom when CYC_I_urom = '1' else
@@ -702,14 +739,14 @@ inst_flash_port : async_port_wb
 		ACK_O		=> ACK_O_flash,
 		SRDY_O		=> SRDY_O_flash,
 		MRDY_I		=> MRDY_O,
-		ADDR_I		=> flash_addr,
+		ADDR_I		=> ADDR_I_flash,
 		DAT_I		=> MDAT_O,
 		DAT_O		=> SDAT_O_flash,
-		async_a		=> sys_flash_a,
-		async_d		=> sys_flash_d,
+		async_a		=> flash_a,
+		async_d		=> sys_flash_ssram_d,
 		async_cs	=> sys_flash_ce,
-		async_wr	=> sys_flash_wrn,
-		async_rd	=> sys_flash_rdn,
+		async_wr	=> flash_we_n,
+		async_rd	=> flash_oe_n,
 		async_rst	=> sys_flash_rstn
 	);
 
@@ -730,7 +767,7 @@ inst_usb_port : async_port_wb
 		ACK_O		=> ACK_O_usb,
 		SRDY_O		=> SRDY_O_usb,
 		MRDY_I		=> MRDY_O,
-		ADDR_I		=> usb_addr,
+		ADDR_I		=> ADDR_I_usb,
 		DAT_I		=> MDAT_O,
 		DAT_O		=> SDAT_O_usb,
 		async_a		=> sys_usb_a,
@@ -763,6 +800,44 @@ inst_uart_wb : uart_wb
 	);
 
 
+inst_ssram_frontend_wb : entity work.ssram_frontend_wb
+	GENERIC MAP
+	(
+		addr_width		=> 25,
+		data_width		=> 32,
+		parity_width	=> 4
+	)
+	PORT MAP
+	(
+		-- J-Bus domain
+		RST_I		=> rst,
+		CLK_I		=> clk,
+		CYC_I		=> CYC_I_ssram,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_ssram,
+		SRDY_O		=> SRDY_O_ssram,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_I_ssram,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_ssram,
+		
+		-- Sync SRAM domain
+		ssram_clk_i	=> ssram_clk,
+		ssram_cke_n	=> sys_ssram_cke_n,
+		ssram_ce_n	=> sys_ssram_ce_n,
+		ssram_oe_n	=> ssram_oe_n,
+		ssram_we_n	=> ssram_we_n,
+		ssram_adv	=> sys_ssram_adv,
+		ssram_mode	=> sys_ssram_mode,
+		ssram_zz	=> sys_ssram_zz,
+		ssram_a		=> ssram_a,
+		ssram_d		=> sys_flash_ssram_d,
+		ssram_dp	=> sys_ssram_dp,
+		ssram_bw_n	=> sys_ssram_bw_n
+	);
+
 inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
 	GENERIC MAP
 	(
@@ -829,9 +904,9 @@ inst_vga_frontend : vga_frontend
 	(
 		sys_freq					=> 100E6,
 		fifo_depth					=> 2048,
-		fifo_almost_full_thresh		=> 2000,
-		fifo_almost_empty_thresh	=> 1600,
-		tsvga						=> ts_vga_800_600_72
+		fifo_almost_full_thresh		=> 1920,
+		fifo_almost_empty_thresh	=> 128,
+		tsvga						=> ts_vga_testbench
 	)
 	PORT MAP
 	(
@@ -874,5 +949,48 @@ inst_vga_frontend : vga_frontend
 		vga_vsync		=> sys_vga_vsync	
 	);
 
+ssram_bufg: bufg
+	port map
+	(
+		o  => ssram_clk,  
+		i  => dcm_clk0
+	);
+
+inst_DCM_BASE_0 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => open,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => dcm_locked,     -- DCM LOCK status output
+		CLKFB => sys_ssram_clk_fb,       -- DCM clock feedback
+		CLKIN => clk,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => rst            -- DCM asynchronous reset input
+	);
+
 	------------------------------------------------------------------
 END;
diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
index 446816e..0db26b1 100644
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ b/projects/mips_sys/src/tb_mips_sys.vhd
@@ -83,13 +83,25 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 	signal sys_usb_rstn			: std_logic;
 	signal sys_usb_int			: std_logic := '0';
 	
-	signal sys_flash_d			: word_t;
-	signal sys_flash_a			: unsigned(24 downto 0);
+	signal sys_flash_ssram_d	: word_t;
+	signal sys_flash_ssram_a	: unsigned(24 downto 0);
+	signal sys_flash_ssram_we_n	: std_logic;
+	signal sys_flash_ssram_oe_n	: std_logic;
+
 	signal sys_flash_ce			: std_logic;
-	signal sys_flash_wrn		: std_logic;
-	signal sys_flash_rdn		: std_logic;
 	signal sys_flash_rstn		: std_logic;
 	signal sys_flash_byten		: std_logic;
+
+	signal sys_ssram_clk_fb		: std_logic;
+	signal sys_ssram_clk		: std_logic;
+	signal sys_ssram_cke_n		: std_logic;
+	signal sys_ssram_ce_n		: std_logic;
+	signal sys_ssram_bw_n		: unsigned(3 downto 0);
+	signal sys_ssram_dp			: unsigned(3 downto 0);
+	signal sys_ssram_adv		: std_logic;
+	signal sys_ssram_mode		: std_logic;
+	signal sys_ssram_zz			: std_logic;
+
 	signal flash_reg			: word_t;
 
 	type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
@@ -105,60 +117,92 @@ uut: entity work.mips_sys
 --	)
 	PORT MAP
 	(
-		sys_rst_n_in => sys_rst_n_in,
-		sys_clk_in => sys_clk_in,
-		sys_btn => btn,
-		sys_dip => dip,
-		sys_led => led,
+		sys_rst_n_in			=> sys_rst_n_in,
+		sys_clk_in				=> sys_clk_in,
+		sys_btn					=> btn,
+		sys_dip					=> dip,
+		sys_led					=> led,
 
-		sys_rx => sys_rx,
-		sys_tx => sys_tx,
+		sys_rx					=> sys_rx,
+		sys_tx					=> sys_tx,
 
-		sys_lcd_d => sys_lcd_d,
-		sys_lcd_e => sys_lcd_e,
-		sys_lcd_rs => sys_lcd_rs,
-		sys_lcd_rw => sys_lcd_rw,
+		sys_lcd_d				=> sys_lcd_d,
+		sys_lcd_e				=> sys_lcd_e,
+		sys_lcd_rs				=> sys_lcd_rs,
+		sys_lcd_rw				=> sys_lcd_rw,
 
-		sys_user_rom_addr => sys_user_rom_addr,
-		sys_user_rom_din => sys_user_rom_din,
-		sys_user_rom_en => sys_user_rom_en,
-		sys_user_rom_clk => sys_user_rom_clk,
+		sys_user_rom_addr		=> sys_user_rom_addr,
+		sys_user_rom_din		=> sys_user_rom_din,
+		sys_user_rom_en			=> sys_user_rom_en,
+		sys_user_rom_clk		=> sys_user_rom_clk,
 
-		sys_sdr_clk_p => sys_sdr_clk_p,
-		sys_sdr_clk_n => sys_sdr_clk_n,
-		sys_sdr_cke_q => sys_sdr_cke_q,
-		sys_sdr_clk_fb => sys_sdr_clk_fb,
-		sys_sdr_cs_qn => sys_sdr_cs_qn,
-		sys_sdr_ras_qn => sys_sdr_ras_qn,
-		sys_sdr_cas_qn => sys_sdr_cas_qn,
-		sys_sdr_we_qn => sys_sdr_we_qn,
-		sys_sdr_dm_q => sys_sdr_dm_q,
-		sys_sdr_dqs_q => sys_sdr_dqs_q,
-		sys_sdr_ba_q => sys_sdr_ba_q,
-		sys_sdr_a_q => sys_sdr_a_q,
-		sys_sdr_data => sys_sdr_data,
+		sys_sdr_clk_p			=> sys_sdr_clk_p,
+		sys_sdr_clk_n			=> sys_sdr_clk_n,
+		sys_sdr_cke_q			=> sys_sdr_cke_q,
+		sys_sdr_clk_fb			=> sys_sdr_clk_fb,
+		sys_sdr_cs_qn			=> sys_sdr_cs_qn,
+		sys_sdr_ras_qn			=> sys_sdr_ras_qn,
+		sys_sdr_cas_qn			=> sys_sdr_cas_qn,
+		sys_sdr_we_qn			=> sys_sdr_we_qn,
+		sys_sdr_dm_q			=> sys_sdr_dm_q,
+		sys_sdr_dqs_q			=> sys_sdr_dqs_q,
+		sys_sdr_ba_q			=> sys_sdr_ba_q,
+		sys_sdr_a_q				=> sys_sdr_a_q,
+		sys_sdr_data			=> sys_sdr_data,
 
-		sys_usb_d		=> sys_usb_d,
-		sys_usb_a		=> sys_usb_a,
-		sys_usb_csn		=> sys_usb_csn,
-		sys_usb_wrn		=> sys_usb_wrn,
-		sys_usb_rdn		=> sys_usb_rdn,
-		sys_usb_rstn	=> sys_usb_rstn,
-		sys_usb_int		=> sys_usb_int,
+		sys_usb_d				=> sys_usb_d,
+		sys_usb_a				=> sys_usb_a,
+		sys_usb_csn				=> sys_usb_csn,
+		sys_usb_wrn				=> sys_usb_wrn,
+		sys_usb_rdn				=> sys_usb_rdn,
+		sys_usb_rstn			=> sys_usb_rstn,
+		sys_usb_int				=> sys_usb_int,
 
-		sys_flash_d		=> sys_flash_d,
-		sys_flash_a		=> sys_flash_a,
-		sys_flash_ce	=> sys_flash_ce,
-		sys_flash_wrn	=> sys_flash_wrn,
-		sys_flash_rdn	=> sys_flash_rdn,
-		sys_flash_rstn	=> sys_flash_rstn,
-		sys_flash_byten	=> sys_flash_byten,
+		sys_flash_ssram_d		=> sys_flash_ssram_d,
+		sys_flash_ssram_a		=> sys_flash_ssram_a,
+		sys_flash_ssram_we_n	=> sys_flash_ssram_we_n,
+		sys_flash_ssram_oe_n	=> sys_flash_ssram_oe_n,
+		sys_flash_ce			=> sys_flash_ce,
+		sys_flash_rstn			=> sys_flash_rstn,
+		sys_flash_byten			=> sys_flash_byten,
 
-		sys_error => sys_error
+		sys_ssram_clk_fb		=> sys_ssram_clk_fb,
+		sys_ssram_clk			=> sys_ssram_clk,
+		sys_ssram_cke_n			=> sys_ssram_cke_n,
+		sys_ssram_ce_n			=> sys_ssram_ce_n,
+		sys_ssram_bw_n			=> sys_ssram_bw_n,
+		sys_ssram_dp			=> sys_ssram_dp,
+		sys_ssram_adv			=> sys_ssram_adv,
+		sys_ssram_mode			=> sys_ssram_mode,
+		sys_ssram_zz			=> sys_ssram_zz,
+
+		sys_error 				=> sys_error
 	);
 
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
+inst_ssram : entity work.cy7c1354
+    PORT MAP 
+    (
+		Dq		=> STD_LOGIC_VECTOR(sys_flash_ssram_d),   	-- Data I/O
+		Dpq		=> STD_LOGIC_VECTOR(sys_ssram_dp),   	-- Data I/O
+		Addr	=> STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)),   	-- Address
+		Mode	=> sys_ssram_mode, 	-- Burst Mode
+		Clk		=> sys_ssram_clk,      -- Clk
+		CEN_n	=> sys_ssram_cke_n,                                   -- CEN#
+		AdvLd_n	=> sys_ssram_adv,                                   -- Adv/Ld#
+		Bwa_n	=> sys_ssram_bw_n(0),                                   -- Bwa#
+		Bwb_n	=> sys_ssram_bw_n(1),                                   -- BWb#
+		Bwc_n	=> sys_ssram_bw_n(2),                                   -- Bwc#
+		Bwd_n	=> sys_ssram_bw_n(3),                                   -- BWd#
+		Rw_n	=> sys_flash_ssram_we_n,                                   -- RW#
+		Oe_n	=> sys_flash_ssram_oe_n,                                   -- OE#
+		Ce1_n	=> sys_ssram_ce_n,                                   -- CE1#
+		Ce2		=> '1',                                   -- CE2
+		Ce3_n	=> '0',                                   -- CE3#
+		Zz		=> sys_ssram_zz
+    );
+    
+-- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16 
       port map (
          dq    => std_logic_vector(sys_sdr_data(15 downto 0)),
          dqs   => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
@@ -174,8 +218,8 @@ uut: entity work.mips_sys
          dm    => std_logic_vector(sys_sdr_dm_q(1 downto 0))
          );
 
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_1 : entity work.mt46v16m16 
+-- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16 
       port map (
          dq    => std_logic_vector(sys_sdr_data(31 downto 16)),
          dqs   => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
@@ -191,7 +235,9 @@ uut: entity work.mips_sys
          dm    => std_logic_vector(sys_sdr_dm_q(3 downto 2))
          );
 
-	sys_sdr_clk_fb   <= sys_sdr_clk_p after 2300 ps;
+	sys_sdr_clk_fb		<= sys_sdr_clk_p after 2300 ps;
+	sys_ssram_clk_fb	<= sys_ssram_clk after 4 ns;
+	
 	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
 
 	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
@@ -222,18 +268,18 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
 		end if;	
 	end process;
 
-FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
+FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
 	begin
-		if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
-			flash_reg <= sys_flash_d;
+		if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
+			flash_reg <= sys_flash_ssram_d;
 		end if;
 	end process;
 		
-FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
+FLASH_READ: process(sys_flash_ce, sys_flash_ssram_oe_n, flash_reg)
 	begin
-		sys_flash_d <= (others => 'Z') after 10 ns;
-		if sys_flash_rdn = '0' and sys_flash_ce = '1' then
-			sys_flash_d <= flash_reg after 10 ns;
+		sys_flash_ssram_d <= (others => 'Z') after 10 ns;
+		if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
+			sys_flash_ssram_d <= flash_reg after 10 ns;
 		end if;
 	end process;