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- removed INT_O_TX from UART. Use now common INT_O for RX/TX

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git-svn-id: http://moon:8086/svn/vhdl/trunk@469 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-05-03 09:30:58 +00:00
parent 134119db33
commit 1c17d74ae1
3 changed files with 17 additions and 16 deletions
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projects/mips_sys/src/mips_sys_sim.vhd
+4 -6
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@@ -266,8 +266,7 @@ ARCHITECTURE behavior OF mips_sys IS
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_RX_O : out STD_LOGIC;
INT_TX_O : out STD_LOGIC;
INT_O : out STD_LOGIC;
ser_rx : in std_logic;
ser_tx : out std_logic
);
@@ -355,7 +354,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal clk270var : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart_rx : std_logic;
signal int_uart : std_logic;
signal locked : std_logic;
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
@@ -575,7 +574,7 @@ int_sample:
process(clk)
begin
if rising_edge(clk) then
INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart & sys_btn(4);
end if;
end process;
@@ -825,8 +824,7 @@ inst_uart_wb : uart_wb
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart,
INT_RX_O => int_uart_rx,
INT_TX_O => open,
INT_O => int_uart,
ser_rx => sys_rx,
ser_tx => sys_tx
);