From 1c17d74ae155ddd84ddbefbe4b16308b9c6b47f2 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 3 May 2009 09:30:58 +0000 Subject: [PATCH] - removed INT_O_TX from UART. Use now common INT_O for RX/TX Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@469 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/uart/uart_wb.vhd | 6 ++---- projects/mips_sys/src/mips_sys.vhd | 17 +++++++++++------ projects/mips_sys/src/mips_sys_sim.vhd | 10 ++++------ 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd index 4d39c2f..0d69a0d 100644 --- a/lib/uart/uart_wb.vhd +++ b/lib/uart/uart_wb.vhd @@ -17,8 +17,7 @@ ENTITY uart_wb IS ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); - INT_RX_O : out STD_LOGIC; - INT_TX_O : out STD_LOGIC; + INT_O : out STD_LOGIC; ser_rx : in std_logic; ser_tx : out std_logic ); @@ -177,7 +176,6 @@ inst_uart_rx: uart_rx ); uart_status_port <= '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - INT_RX_O <= rx_data_present and rx_int_en; - INT_TX_O <= not tx_full and tx_int_en; + INT_O <= (rx_data_present and rx_int_en) or (not tx_full and tx_int_en); end behavior; diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 1b57adc..76e7bc8 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -222,8 +222,7 @@ ARCHITECTURE behavior OF mips_sys IS ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); - INT_RX_O : out STD_LOGIC; - INT_TX_O : out STD_LOGIC; + INT_O : out STD_LOGIC; ser_rx : in std_logic; ser_tx : out std_logic ); @@ -311,7 +310,7 @@ ARCHITECTURE behavior OF mips_sys IS signal clk270var : std_logic; signal rst_in : std_logic; signal int_timer : std_logic; - signal int_uart_rx : std_logic; + signal int_uart : std_logic; signal locked : std_logic; signal usb_addr : unsigned(31 downto 0); signal flash_addr : unsigned(31 downto 0); @@ -425,6 +424,13 @@ ARCHITECTURE behavior OF mips_sys IS BEGIN + ------------------------------------ + -- GPO1 bits used for + -- 0 : USB reset + -- 1 : USB interrupt enable + -- 2 : AC97 interrupt enable + -- others : reserved + ------------------------------------ eb <= sys_dip(7); gpi0(4 downto 0) <= sys_btn; gpi1(7 downto 0) <= sys_dip; @@ -485,7 +491,7 @@ int_sample: process(clk) begin if rising_edge(clk) then - INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4); + INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & int_uart & sys_btn(4); end if; end process; @@ -726,8 +732,7 @@ inst_uart_wb : uart_wb ADDR_I => ADDR_O, DAT_I => MDAT_O, DAT_O => SDAT_O_uart, - INT_RX_O => int_uart_rx, - INT_TX_O => open, + INT_O => int_uart, ser_rx => sys_rx, ser_tx => sys_tx ); diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 8f3b0d4..e6d02a0 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -266,8 +266,7 @@ ARCHITECTURE behavior OF mips_sys IS ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); - INT_RX_O : out STD_LOGIC; - INT_TX_O : out STD_LOGIC; + INT_O : out STD_LOGIC; ser_rx : in std_logic; ser_tx : out std_logic ); @@ -355,7 +354,7 @@ ARCHITECTURE behavior OF mips_sys IS signal clk270var : std_logic; signal rst_in : std_logic; signal int_timer : std_logic; - signal int_uart_rx : std_logic; + signal int_uart : std_logic; signal locked : std_logic; signal ac97_rstn : std_logic; signal flash_rstn : std_logic; @@ -575,7 +574,7 @@ int_sample: process(clk) begin if rising_edge(clk) then - INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4); + INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart & sys_btn(4); end if; end process; @@ -825,8 +824,7 @@ inst_uart_wb : uart_wb ADDR_I => ADDR_O, DAT_I => MDAT_O, DAT_O => SDAT_O_uart, - INT_RX_O => int_uart_rx, - INT_TX_O => open, + INT_O => int_uart, ser_rx => sys_rx, ser_tx => sys_tx );