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- added function for I/D-cache invalidate

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- added functions for LWC0 and SWC0
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git-svn-id: http://moon:8086/svn/vhdl/trunk@443 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-04-15 14:03:20 +00:00
parent cf72d81cd3
commit 1be58489b0
2 changed files with 75 additions and 7 deletions
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lib/CPUs/MIPS/bsp/examples/libsys.c
+65 -7
View File
@@ -13,7 +13,7 @@ UINT32 CP0_SR_read(void)
{
UINT32 result;
__asm
__asm__
(
"mfc0 %[val], $12\n"
: [val] "=r" (result)
@@ -24,7 +24,7 @@ UINT32 CP0_SR_read(void)
void CP0_SR_write(UINT32 val)
{
__asm
__asm__
(
"mtc0 %[val], $12\n"
: /* no output */
@@ -36,7 +36,7 @@ UINT32 CP0_CR_read(void)
{
UINT32 result;
__asm
__asm__
(
"mfc0 %[val], $13\n"
: [val] "=r" (result)
@@ -47,7 +47,7 @@ UINT32 CP0_CR_read(void)
void CP0_CR_write(UINT32 val)
{
__asm
__asm__
(
"mtc0 %[val], $13\n"
:
@@ -59,7 +59,7 @@ UINT32 CP0_TR_read(void)
{
UINT32 result;
__asm
__asm__
(
"mfc0 %[val], $31\n"
: [val] "=r" (result)
@@ -70,7 +70,7 @@ UINT32 CP0_TR_read(void)
void CP0_TR_write(UINT32 val)
{
__asm
__asm__
(
"mtc0 %[val], $31\n"
:
@@ -82,7 +82,7 @@ UINT32 CP0_PRID_read(void)
{
UINT32 result;
__asm
__asm__
(
"mfc0 %[val], $15\n"
: [val] "=r" (result)
@@ -91,6 +91,64 @@ UINT32 CP0_PRID_read(void)
return result;
}
void CP0_TR_write_ptr(UINT32* pPtr)
{
__asm__
(
"swc0 $31, 0(%[pPtr])\n"
:
: [pPtr] "r" (pPtr)
);
}
void CP0_TR_read_ptr(UINT32* pPtr)
{
__asm__
(
"lwc0 $31, 0(%[pPtr])\n"
:
: [pPtr] "r" (pPtr)
);
}
void ICACHE_invalidate_all(void)
{
__asm__
(
"cop0 32\n"
);
}
void ICACHE_invalidate_at(UINT32* pPtr)
{
__asm__
(
"mtc0 %[pPtr], $31\n"
"cop0 33\n"
:
: [pPtr] "r" (pPtr)
);
}
void DCACHE_invalidate_all(void)
{
__asm__
(
"cop0 34\n"
);
}
void DCACHE_invalidate_at(UINT32* pPtr)
{
__asm__
(
"mtc0 %[pPtr], $31\n"
"cop0 35\n"
:
: [pPtr] "r" (pPtr)
);
}
// ---------------------------------------------------------------------------------
char readchar(void)
{