From 1be58489b081132d0fefa12f54aacc14a1f7f360 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 15 Apr 2009 14:03:20 +0000
Subject: [PATCH] - added function for I/D-cache invalidate - added functions
 for LWC0 and SWC0 Committed on the Free edition of March Hare Software CVSNT
 Server. Upgrade to CVS Suite for more features and support:
 http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@443 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/bsp/examples/libsys.c | 72 ++++++++++++++++++++++++++---
 lib/CPUs/MIPS/bsp/examples/libsys.h | 10 ++++
 2 files changed, 75 insertions(+), 7 deletions(-)

diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.c b/lib/CPUs/MIPS/bsp/examples/libsys.c
index eda27e8..32ddad9 100644
--- a/lib/CPUs/MIPS/bsp/examples/libsys.c
+++ b/lib/CPUs/MIPS/bsp/examples/libsys.c
@@ -13,7 +13,7 @@ UINT32 CP0_SR_read(void)
 {
 	UINT32 result;
 
-	__asm
+	__asm__
 	(
 		"mfc0   %[val], $12\n"
 		: [val] "=r" (result)
@@ -24,7 +24,7 @@ UINT32 CP0_SR_read(void)
 
 void CP0_SR_write(UINT32 val)
 {
-	__asm
+	__asm__
 	(
 		"mtc0   %[val], $12\n"
 		: /* no output */
@@ -36,7 +36,7 @@ UINT32 CP0_CR_read(void)
 {
 	UINT32 result;
 
-	__asm
+	__asm__
 	(
 		"mfc0   %[val], $13\n"
 		: [val] "=r" (result)
@@ -47,7 +47,7 @@ UINT32 CP0_CR_read(void)
 
 void CP0_CR_write(UINT32 val)
 {
-	__asm
+	__asm__
 	(
 		"mtc0   %[val], $13\n"
 		:
@@ -59,7 +59,7 @@ UINT32 CP0_TR_read(void)
 {
 	UINT32 result;
 
-	__asm
+	__asm__
 	(
 		"mfc0   %[val], $31\n"
 		: [val] "=r" (result)
@@ -70,7 +70,7 @@ UINT32 CP0_TR_read(void)
 
 void CP0_TR_write(UINT32 val)
 {
-	__asm
+	__asm__
 	(
 		"mtc0   %[val], $31\n"
 		:
@@ -82,7 +82,7 @@ UINT32 CP0_PRID_read(void)
 {
 	UINT32 result;
 
-	__asm
+	__asm__
 	(
 		"mfc0   %[val], $15\n"
 		: [val] "=r" (result)
@@ -91,6 +91,64 @@ UINT32 CP0_PRID_read(void)
 	return result;
 }
 
+void CP0_TR_write_ptr(UINT32* pPtr)
+{
+	__asm__
+	(
+		"swc0   $31, 0(%[pPtr])\n"
+		:
+		: [pPtr] "r" (pPtr)
+	);
+}
+
+void CP0_TR_read_ptr(UINT32* pPtr)
+{
+	__asm__
+	(
+		"lwc0   $31, 0(%[pPtr])\n"
+		:
+		: [pPtr] "r" (pPtr)
+	);
+}
+
+void ICACHE_invalidate_all(void)
+{
+	__asm__
+	(
+		"cop0	32\n"
+	);
+}
+
+void ICACHE_invalidate_at(UINT32* pPtr)
+{
+	__asm__
+	(
+		"mtc0   %[pPtr], $31\n"
+		"cop0	33\n"
+		:
+		: [pPtr] "r" (pPtr)
+	);
+}
+
+void DCACHE_invalidate_all(void)
+{
+	__asm__
+	(
+		"cop0	34\n"
+	);
+}
+
+void DCACHE_invalidate_at(UINT32* pPtr)
+{
+	__asm__
+	(
+		"mtc0   %[pPtr], $31\n"
+		"cop0	35\n"
+		:
+		: [pPtr] "r" (pPtr)
+	);
+}
+
 // ---------------------------------------------------------------------------------
 char readchar(void)
 {
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.h b/lib/CPUs/MIPS/bsp/examples/libsys.h
index dced397..25b7b79 100644
--- a/lib/CPUs/MIPS/bsp/examples/libsys.h
+++ b/lib/CPUs/MIPS/bsp/examples/libsys.h
@@ -24,6 +24,10 @@
 #define	sys_usb_ctrl	sys_gpio1
 #define	sys_timer_usec	0xA0000008
 #define	sys_timer_sec	0xA000000C
+#define	sys_itim_ctrl	0xA0000010
+#define	sys_itim_stat	0xA0000014
+#define	sys_itim_cnt	0xA0000018
+#define	sys_itim_cmp	0xA000001C
 #define	sys_uart_data	0xA0010000
 #define	sys_uart_stat	0xA0010004
 #define	sys_uart_baud	0xA0010008
@@ -65,6 +69,12 @@ void CP0_CR_write(UINT32 val);
 UINT32 CP0_PRID_read(void);
 UINT32 CP0_TR_read(void);
 void CP0_TR_write(UINT32 val);
+void CP0_TR_write_ptr(UINT32* pPtr);
+void CP0_TR_read_ptr(UINT32* pPtr);
+void ICACHE_invalidate_all(void);
+void ICACHE_invalidate_at(UINT32* pPtr);
+void DCACHE_invalidate_all(void);
+void DCACHE_invalidate_at(UINT32* pPtr);
 
 char readchar(void);
 void writechar(char c);