- increased window for RX/TX-Data to 32 kByte. Offset is at 0x8000..0x8FFC
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@909 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -64,19 +64,40 @@ ARCHITECTURE behavior OF emac_top_jb IS
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signal ready : std_logic;
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signal read : std_logic;
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signal write : std_logic;
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signal data_read : std_logic;
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signal data_write : std_logic;
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signal reg_read : std_logic;
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signal reg_write : std_logic;
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signal reg_addr : unsigned(3 downto 0);
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begin
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SRDY_O <= CYC_I and ready;
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mii_gtx_clk <= '0';
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mii_gtx_clk <= '0';
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ready <= not tx_ctrl_in.pkt_alloc_en;
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SRDY_O <= CYC_I and ready;
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read <= STB_I and CYC_I and not WE_I;
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write <= STB_I and CYC_I and WE_I;
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data_read <= read and ADDR_I(15);
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data_write <= write and ADDR_I(15);
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reg_read <= read and not ADDR_I(15);
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reg_write <= write and not ADDR_I(15);
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reg_addr <= ADDR_I(5 downto 2);
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ready <= not tx_ctrl_in.pkt_alloc_en;
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tx_din_vld <= data_write;
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tx_din <= DAT_I;
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rx_ctrl_in.pkt_read_en <= data_read;
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------------------------------------------------------------------
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registers_write:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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tx_din_vld <= '0';
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tx_ctrl_in.pkt_alloc_en <= '0';
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tx_ctrl_in.pkt_commit_en <= '0';
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tx_ctrl_in.reset <= '0';
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@@ -93,9 +114,11 @@ registers_write:
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rx_ctrl_in.Gbps_en <= '0';
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tx_ctrl_in.fcs_gen_en <= '0';
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rx_ctrl_in.fcs_chk_en <= '0';
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elsif (STB_I and CYC_I and WE_I) = '1' then
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case ADDR_I(5 downto 2) is
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elsif reg_write = '1' then
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-- 0x0000 .. 0x003C
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case reg_addr is
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-- 0x0000
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when "0000" =>
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rx_ctrl_in.reset <= DAT_I(31);
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@@ -105,10 +128,10 @@ registers_write:
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rx_ctrl_in.pkt_req_en <= DAT_I(17);
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rx_ctrl_in.pkt_free_en <= DAT_I(16);
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rx_int_en <= DAT_I(4);
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-- 0x0004
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-- rx_size R/O
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-- 0x0008
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when "0010" =>
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tx_ctrl_in.reset <= DAT_I(31);
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@@ -117,14 +140,14 @@ registers_write:
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tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
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tx_ctrl_in.pkt_commit_en <= DAT_I(16);
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tx_int_en <= DAT_I(4);
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-- 0x000C
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when "0011" =>
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tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
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-- 0x0010
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-- Gap
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-- 0x0014
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-- Gap
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@@ -134,20 +157,18 @@ registers_write:
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rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
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rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
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rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
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-- 0x001C
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when "0111" =>
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rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
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rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
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-- 0x0020 .. 0x003C
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-- Window for TX-Data (8 words)
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-- For cached burst access, this must be greater or equal to D-Cache line size
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when others =>
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tx_din_vld <= '1';
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tx_din <= DAT_I;
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-- Gap
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when others => null;
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end case;
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end if;
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end if;
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end process;
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@@ -156,11 +177,12 @@ registers_read:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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rx_ctrl_in.pkt_read_en <= '0';
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ACK_O <= rx_dout_vld and CYC_I and not WE_I;
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ACK_O <= rx_dout_vld;
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DAT_O <= rx_dout;
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if (STB_I and CYC_I) = '1' and WE_I = '0' then
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case ADDR_I(5 downto 2) is
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if reg_read = '1' then
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-- 0x0000 .. 0x003C
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case reg_addr is
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-- 0x0000
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when "0000" =>
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@@ -175,7 +197,7 @@ registers_read:
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DAT_O(17) <= rx_ctrl_out.pkt_valid;
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DAT_O(16) <= rx_ctrl_out.pkt_avail;
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DAT_O(4) <= rx_int_en;
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-- 0x0004
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when "0001" =>
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ACK_O <= '1';
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@@ -192,7 +214,7 @@ registers_read:
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DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
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DAT_O(16) <= tx_ctrl_out.pkt_armed;
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DAT_O(4) <= tx_int_en;
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-- 0x000C
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when "0011" =>
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ACK_O <= '1';
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@@ -200,7 +222,7 @@ registers_read:
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-- 0x0010
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-- Gap
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-- 0x0014
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-- Gap
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@@ -208,19 +230,18 @@ registers_read:
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when "0110" =>
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ACK_O <= '1';
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DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
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-- 0x001C
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when "0111" =>
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ACK_O <= '1';
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DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
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-- 0x0020 .. 0x003C
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-- Window for RX-Data (8 words)
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-- For cached burst access, this must be greater or equal to D-Cache line size
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when others =>
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rx_ctrl_in.pkt_read_en <= '1';
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-- Gap
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when others => null;
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end case;
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end if;
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end if;
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end process;
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@@ -88,7 +88,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
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constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
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constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
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constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
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constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010";
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constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000";
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BEGIN
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