From 197e65fc28c92eb329f143c469708162aa54f6f1 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 10 Apr 2010 12:04:18 +0000 Subject: [PATCH] - increased window for RX/TX-Data to 32 kByte. Offset is at 0x8000..0x8FFC Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@909 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/emac_top_jb.vhd | 87 ++++++++++++++++++++------------- lib/emac/src/tb_emac_top_jb.vhd | 2 +- 2 files changed, 55 insertions(+), 34 deletions(-) diff --git a/lib/emac/src/emac_top_jb.vhd b/lib/emac/src/emac_top_jb.vhd index 17d6537..44c2e8d 100644 --- a/lib/emac/src/emac_top_jb.vhd +++ b/lib/emac/src/emac_top_jb.vhd @@ -64,19 +64,40 @@ ARCHITECTURE behavior OF emac_top_jb IS signal ready : std_logic; + signal read : std_logic; + signal write : std_logic; + signal data_read : std_logic; + signal data_write : std_logic; + signal reg_read : std_logic; + signal reg_write : std_logic; + + signal reg_addr : unsigned(3 downto 0); + begin - SRDY_O <= CYC_I and ready; - mii_gtx_clk <= '0'; + mii_gtx_clk <= '0'; - ready <= not tx_ctrl_in.pkt_alloc_en; + SRDY_O <= CYC_I and ready; + read <= STB_I and CYC_I and not WE_I; + write <= STB_I and CYC_I and WE_I; + data_read <= read and ADDR_I(15); + data_write <= write and ADDR_I(15); + reg_read <= read and not ADDR_I(15); + reg_write <= write and not ADDR_I(15); + reg_addr <= ADDR_I(5 downto 2); + + ready <= not tx_ctrl_in.pkt_alloc_en; + + tx_din_vld <= data_write; + tx_din <= DAT_I; + + rx_ctrl_in.pkt_read_en <= data_read; ------------------------------------------------------------------ registers_write: process(CLK_I) begin if rising_edge(CLK_I) then - tx_din_vld <= '0'; tx_ctrl_in.pkt_alloc_en <= '0'; tx_ctrl_in.pkt_commit_en <= '0'; tx_ctrl_in.reset <= '0'; @@ -93,9 +114,11 @@ registers_write: rx_ctrl_in.Gbps_en <= '0'; tx_ctrl_in.fcs_gen_en <= '0'; rx_ctrl_in.fcs_chk_en <= '0'; - elsif (STB_I and CYC_I and WE_I) = '1' then - case ADDR_I(5 downto 2) is - + elsif reg_write = '1' then + + -- 0x0000 .. 0x003C + case reg_addr is + -- 0x0000 when "0000" => rx_ctrl_in.reset <= DAT_I(31); @@ -105,10 +128,10 @@ registers_write: rx_ctrl_in.pkt_req_en <= DAT_I(17); rx_ctrl_in.pkt_free_en <= DAT_I(16); rx_int_en <= DAT_I(4); - + -- 0x0004 -- rx_size R/O - + -- 0x0008 when "0010" => tx_ctrl_in.reset <= DAT_I(31); @@ -117,14 +140,14 @@ registers_write: tx_ctrl_in.pkt_alloc_en <= DAT_I(17); tx_ctrl_in.pkt_commit_en <= DAT_I(16); tx_int_en <= DAT_I(4); - + -- 0x000C when "0011" => tx_ctrl_in.tx_size <= DAT_I(15 downto 0); - + -- 0x0010 -- Gap - + -- 0x0014 -- Gap @@ -134,20 +157,18 @@ registers_write: rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16); rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8); rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0); - + -- 0x001C when "0111" => rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24); rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16); -- 0x0020 .. 0x003C - -- Window for TX-Data (8 words) - -- For cached burst access, this must be greater or equal to D-Cache line size - when others => - tx_din_vld <= '1'; - tx_din <= DAT_I; - + -- Gap + when others => null; + end case; + end if; end if; end process; @@ -156,11 +177,12 @@ registers_read: process(CLK_I) begin if rising_edge(CLK_I) then - rx_ctrl_in.pkt_read_en <= '0'; - ACK_O <= rx_dout_vld and CYC_I and not WE_I; + ACK_O <= rx_dout_vld; DAT_O <= rx_dout; - if (STB_I and CYC_I) = '1' and WE_I = '0' then - case ADDR_I(5 downto 2) is + if reg_read = '1' then + + -- 0x0000 .. 0x003C + case reg_addr is -- 0x0000 when "0000" => @@ -175,7 +197,7 @@ registers_read: DAT_O(17) <= rx_ctrl_out.pkt_valid; DAT_O(16) <= rx_ctrl_out.pkt_avail; DAT_O(4) <= rx_int_en; - + -- 0x0004 when "0001" => ACK_O <= '1'; @@ -192,7 +214,7 @@ registers_read: DAT_O(17) <= tx_ctrl_out.pkt_alloc_req; DAT_O(16) <= tx_ctrl_out.pkt_armed; DAT_O(4) <= tx_int_en; - + -- 0x000C when "0011" => ACK_O <= '1'; @@ -200,7 +222,7 @@ registers_read: -- 0x0010 -- Gap - + -- 0x0014 -- Gap @@ -208,19 +230,18 @@ registers_read: when "0110" => ACK_O <= '1'; DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3); - + -- 0x001C when "0111" => ACK_O <= '1'; DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000"; - + -- 0x0020 .. 0x003C - -- Window for RX-Data (8 words) - -- For cached burst access, this must be greater or equal to D-Cache line size - when others => - rx_ctrl_in.pkt_read_en <= '1'; - + -- Gap + when others => null; + end case; + end if; end if; end process; diff --git a/lib/emac/src/tb_emac_top_jb.vhd b/lib/emac/src/tb_emac_top_jb.vhd index dddf042..b32ae9c 100644 --- a/lib/emac/src/tb_emac_top_jb.vhd +++ b/lib/emac/src/tb_emac_top_jb.vhd @@ -88,7 +88,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004"; constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008"; constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C"; - constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010"; + constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_8000"; BEGIN