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- minor mods to accu_ld_pipe

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git-svn-id: http://moon:8086/svn/vhdl/trunk@195 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2009-01-04 13:56:07 +00:00
parent bc4c015150
commit 1738a6c0b6
1 changed files with 2 additions and 2 deletions
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lib/filter/src/fir_semi_parallel.vhd
+2 -2
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@@ -96,7 +96,7 @@ architecture Behavioral of fir_semi_parallel is
SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
signal accu_load : std_logic;
signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0);
signal accu_ld_pipe : unsigned(input_latency+coef_latency+pipe_latency downto 0);
signal vld_pipe : unsigned(1 downto 0);
-------------------------------------------------------------------------------
@@ -130,7 +130,7 @@ accu_load_pipe:
process(clk)
begin
if rising_edge(clk) then
accu_ld_pipe(0) <= ce0;
accu_ld_pipe(0) <= ce_array(nstages-1);
for i in 1 to accu_ld_pipe'length-1 loop
if rst = '1' then
accu_ld_pipe(i) <= '0';