diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index f1c9898..14ecc82 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -96,7 +96,7 @@ architecture Behavioral of fir_semi_parallel is
 	SIGNAL accu			: sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
 	signal accu_load	: std_logic;
 
-	signal accu_ld_pipe	: unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0);
+	signal accu_ld_pipe	: unsigned(input_latency+coef_latency+pipe_latency downto 0);
 	signal vld_pipe		: unsigned(1 downto 0);
 	
 	-------------------------------------------------------------------------------
@@ -130,7 +130,7 @@ accu_load_pipe:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			accu_ld_pipe(0)	<= ce0;
+			accu_ld_pipe(0)	<= ce_array(nstages-1);
 			for i in 1 to accu_ld_pipe'length-1 loop
 				if rst = '1' then
 					accu_ld_pipe(i) <= '0';