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- Inhibit RAM write if FIFO is full

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- Inhibit update of output if last word is read


git-svn-id: http://moon:8086/svn/vhdl/trunk@38 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-10 21:23:27 +00:00
parent 3015a0c6de
commit 1493e3e779
1 changed files with 25 additions and 19 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd
+11 -5
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@@ -52,17 +52,21 @@ end fifo_sync;
architecture Behavioral of fifo_sync is architecture Behavioral of fifo_sync is
signal mem_we : STD_LOGIC; signal mem_wr_en : STD_LOGIC;
signal mem_rd_en : STD_LOGIC;
signal ptr_w : unsigned (addr_width-1 downto 0); signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0); signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC; signal full : STD_LOGIC;
signal empty : STD_LOGIC; signal empty : STD_LOGIC;
signal almost_full : STD_LOGIC; signal almost_full : STD_LOGIC;
signal almost_empty : STD_LOGIC; signal almost_empty : STD_LOGIC;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
begin begin
mem_we <= we; mem_wr_en <= not full;
mem_rd_en <= not pre_empty;
fifo_full <= full; fifo_full <= full;
fifo_empty <= empty; fifo_empty <= empty;
fifo_afull <= almost_full; fifo_afull <= almost_full;
@@ -85,6 +89,8 @@ begin
ptr_r => ptr_r, ptr_r => ptr_r,
fifo_full => full, fifo_full => full,
fifo_empty => empty, fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => almost_full, fifo_afull => almost_full,
fifo_aempty => almost_empty fifo_aempty => almost_empty
@@ -98,9 +104,9 @@ begin
PORT MAP( PORT MAP(
clka => clk, clka => clk,
clkb => clk, clkb => clk,
en_a => '1', en_a => mem_wr_en,
en_b => '1', en_b => mem_rd_en,
we_a => mem_we, we_a => we,
addr_a => ptr_w, addr_a => ptr_w,
addr_b => ptr_r, addr_b => ptr_r,
din_a => data_w, din_a => data_w,