- Inhibit RAM write if FIFO is full

- Inhibit update of output if last word is read


git-svn-id: http://moon:8086/svn/vhdl/trunk@38 cc03376c-175c-47c8-b038-4cd826a8556b

lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd

@@ -52,21 +52,25 @@ end fifo_sync;
 
 architecture Behavioral of fifo_sync is
 	
-	signal mem_we		: STD_LOGIC;
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
 	signal ptr_w		: unsigned (addr_width-1 downto 0);
 	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: STD_LOGIC;
 	signal empty		: STD_LOGIC;
 	signal almost_full	: STD_LOGIC;
 	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
 	
 begin
 
-	mem_we <= we;
-	fifo_full <= full;
-	fifo_empty <= empty;
-	fifo_afull <= almost_full;
-	fifo_aempty <= almost_empty;
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
 
 	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
 	GENERIC MAP
@@ -77,16 +81,18 @@ begin
 	)
 	PORT MAP
 	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	we,
-		re			=>	re,
-		ptr_w		=>	ptr_w,
-		ptr_r		=>	ptr_r,
-		fifo_full	=>	full,
-		fifo_empty	=>	empty,
-		fifo_afull	=>	almost_full,
-		fifo_aempty	=>	almost_empty
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
 
 	);
 
@@ -98,9 +104,9 @@ begin
 	PORT MAP(
 		clka		=> clk,
 		clkb		=> clk,
-		en_a		=> '1',
-		en_b		=> '1',
-		we_a		=> mem_we,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
 		addr_a		=> ptr_w,
 		addr_b		=> ptr_r,
 		din_a		=> data_w,