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- made time specs in nano seconds, thus independent of clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@721 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 15:43:04 +00:00
parent 4cfe77786b
commit 149140cad7
4 changed files with 93 additions and 80 deletions
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lib/misc/async_port_wb.vhd
+18 -17
View File
@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.14 2010-02-07 15:42:47 Jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -10,6 +10,7 @@ use work.async_types.all;
entity async_port_wb is entity async_port_wb is
Generic Generic
( (
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32; addr_width : natural := 32;
data_width : natural := 32; data_width : natural := 32;
byte_sel_width : natural := 4; byte_sel_width : natural := 4;
@@ -72,9 +73,9 @@ architecture Behavioral of async_port_wb is
------------------------------------------------------------------ ------------------------------------------------------------------
begin begin
ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure; ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure; ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure; ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo; SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I; en <= CYC_I and STB_I;
@@ -110,7 +111,7 @@ architecture Behavioral of async_port_wb is
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read) process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin begin
cycle_reload <= async_timespec.ncyc_pulse_rst; cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk_hz);
cc_rst <= '0'; cc_rst <= '0';
as.rst <= '0'; as.rst <= '0';
as.cs <= '0'; as.cs <= '0';
@@ -138,17 +139,17 @@ architecture Behavioral of async_port_wb is
if en = '1' then if en = '1' then
as.cs <= '1'; as.cs <= '1';
cc_rst <= '1'; cc_rst <= '1';
if async_timespec.ncyc_leadin = 0 then if to_cycles(async_timespec.T_leadin, f_sysclk_hz) = 0 then
sn <= pulse; sn <= pulse;
if WE_I = '1' then if WE_I = '1' then
cycle_reload <= 0; cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes sn <= leadin; -- always lead-in for writes
else else
cycle_reload <= async_timespec.ncyc_pulse_rd-1; cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
as.rd <= '1'; as.rd <= '1';
end if; end if;
else else
cycle_reload <= async_timespec.ncyc_leadin-1; cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk_hz) - 1;
sn <= leadin; sn <= leadin;
end if; end if;
end if; end if;
@@ -162,9 +163,9 @@ architecture Behavioral of async_port_wb is
cc_rst <= '1'; cc_rst <= '1';
sn <= pulse; sn <= pulse;
if WE_I_r = '1' then if WE_I_r = '1' then
cycle_reload <= async_timespec.ncyc_pulse_wr-1; cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) - 1;
else else
cycle_reload <= async_timespec.ncyc_pulse_rd-1; cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
end if; end if;
end if; end if;
@@ -179,17 +180,17 @@ architecture Behavioral of async_port_wb is
ack <= not WE_I_r; ack <= not WE_I_r;
rdy <= do_page_read; rdy <= do_page_read;
if en = '1' and do_page_read = '1' then if en = '1' and do_page_read = '1' then
cycle_reload <= async_timespec.ncyc_pulse_page_rd-1; cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) - 1;
sn <= pulse; sn <= pulse;
elsif async_timespec.ncyc_leadout = 0 then elsif to_cycles(async_timespec.T_leadout, f_sysclk_hz) = 0 then
if async_timespec.ncyc_release = 0 then if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
sn <= idle; sn <= idle;
else else
cycle_reload <= async_timespec.ncyc_release-1; cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
sn <= release; sn <= release;
end if; end if;
else else
cycle_reload <= async_timespec.ncyc_leadout-1; cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk_hz) - 1;
sn <= leadout; sn <= leadout;
end if; end if;
end if; end if;
@@ -199,10 +200,10 @@ architecture Behavioral of async_port_wb is
as.drive_d <= WE_I_r; as.drive_d <= WE_I_r;
if cycle_cnt = 0 then if cycle_cnt = 0 then
cc_rst <= '1'; cc_rst <= '1';
if async_timespec.ncyc_release = 0 then if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
sn <= idle; sn <= idle;
else else
cycle_reload <= async_timespec.ncyc_release-1; cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
sn <= release; sn <= release;
end if; end if;
end if; end if;
lib/misc/async_types.vhd
+19 -7
View File
@@ -28,15 +28,15 @@ USE IEEE.NUMERIC_STD.ALL;
package async_types is package async_types is
type async_timespec_t is record type async_timespec_t is record
ncyc_leadin : natural; T_leadin : real;
ncyc_pulse_rd : natural; T_pulse_rd : real;
ncyc_pulse_wr : natural; T_pulse_wr : real;
ncyc_leadout : natural; T_leadout : real;
ncyc_release : natural; T_release : real;
ncyc_pulse_rst : natural; T_pulse_rst : real;
T_pulse_page_rd : real;
can_page_rd : boolean; can_page_rd : boolean;
nbits_page_rd : natural; nbits_page_rd : natural;
ncyc_pulse_page_rd : natural;
pol_cs : std_logic; pol_cs : std_logic;
pol_oe : std_logic; pol_oe : std_logic;
pol_we : std_logic; pol_we : std_logic;
@@ -44,4 +44,16 @@ package async_types is
pol_rst : std_logic; pol_rst : std_logic;
end record; end record;
function to_cycles(T_ns : real; f_hz : natural) return natural;
end async_types;
package body async_types is
function to_cycles(T_ns : real; f_hz : natural) return natural is
begin
return natural(0.5 + 10.0E-9*T_ns*real(f_hz));
end to_cycles;
end async_types; end async_types;
projects/mips_sys/src/async_defs_sim.vhd
+28 -28
View File
@@ -31,38 +31,38 @@ package async_defs is
constant ts_flash : async_timespec_t := constant ts_flash : async_timespec_t :=
( (
ncyc_leadin => 1, T_leadin => 10.0,
ncyc_pulse_rd => 12, T_pulse_rd => 120.0,
ncyc_pulse_wr => 7, T_pulse_wr => 70.0,
ncyc_leadout => 1, T_leadout => 10.0,
ncyc_release => 4, T_release => 40.0,
ncyc_pulse_rst => 8, T_pulse_rst => 80.0,
can_page_rd => true, T_pulse_page_rd => 30.0,
nbits_page_rd => 4, can_page_rd => true,
ncyc_pulse_page_rd => 3, nbits_page_rd => 4,
pol_cs => '1', pol_cs => '1',
pol_oe => '0', pol_oe => '0',
pol_we => '0', pol_we => '0',
pol_be => '0', pol_be => '0',
pol_rst => '0' pol_rst => '0'
); );
constant ts_usb : async_timespec_t := constant ts_usb : async_timespec_t :=
( (
ncyc_leadin => 1, T_leadin => 10.0,
ncyc_pulse_rd => 6, T_pulse_rd => 60.0,
ncyc_pulse_wr => 6, T_pulse_wr => 60.0,
ncyc_leadout => 1, T_leadout => 10.0,
ncyc_release => 8, T_release => 80.0,
ncyc_pulse_rst => 8, T_pulse_rst => 80.0,
can_page_rd => false, T_pulse_page_rd => 00.0,
nbits_page_rd => 0, can_page_rd => false,
ncyc_pulse_page_rd => 0, nbits_page_rd => 0,
pol_cs => '0', pol_cs => '0',
pol_oe => '0', pol_oe => '0',
pol_we => '0', pol_we => '0',
pol_be => '0', pol_be => '0',
pol_rst => '0' pol_rst => '0'
); );
---------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------
projects/mips_sys/src/sys_types.vhd
+28 -28
View File
@@ -31,38 +31,38 @@ package async_defs is
constant ts_flash : async_timespec_t := constant ts_flash : async_timespec_t :=
( (
ncyc_leadin => 0, T_leadin => 00.0,
ncyc_pulse_rd => 12, T_pulse_rd => 120.0,
ncyc_pulse_wr => 7, T_pulse_wr => 70.0,
ncyc_leadout => 0, T_leadout => 00.0,
ncyc_release => 4, T_release => 40.0,
ncyc_pulse_rst => 8, T_pulse_rst => 80.0,
can_page_rd => true, T_pulse_page_rd => 30.0,
nbits_page_rd => 4, can_page_rd => true,
ncyc_pulse_page_rd => 3, nbits_page_rd => 4,
pol_cs => '1', pol_cs => '1',
pol_oe => '0', pol_oe => '0',
pol_we => '0', pol_we => '0',
pol_be => '0', pol_be => '0',
pol_rst => '0' pol_rst => '0'
); );
constant ts_usb : async_timespec_t := constant ts_usb : async_timespec_t :=
( (
ncyc_leadin => 1, T_leadin => 10.0,
ncyc_pulse_rd => 6, T_pulse_rd => 60.0,
ncyc_pulse_wr => 6, T_pulse_wr => 60.0,
ncyc_leadout => 1, T_leadout => 10.0,
ncyc_release => 8, T_release => 80.0,
ncyc_pulse_rst => 8, T_pulse_rst => 80.0,
can_page_rd => false, T_pulse_page_rd => 00.0,
nbits_page_rd => 0, can_page_rd => false,
ncyc_pulse_page_rd => 0, nbits_page_rd => 0,
pol_cs => '0', pol_cs => '0',
pol_oe => '0', pol_oe => '0',
pol_we => '0', pol_we => '0',
pol_be => '0', pol_be => '0',
pol_rst => '0' pol_rst => '0'
); );
---------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------