From 149140cad7fff64c837e39cf41ab0d1d475eef70 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 7 Feb 2010 15:43:04 +0000 Subject: [PATCH] - made time specs in nano seconds, thus independent of clock Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@721 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/misc/async_port_wb.vhd | 35 ++++++++------- lib/misc/async_types.vhd | 26 ++++++++--- projects/mips_sys/src/async_defs_sim.vhd | 56 ++++++++++++------------ projects/mips_sys/src/sys_types.vhd | 56 ++++++++++++------------ 4 files changed, 93 insertions(+), 80 deletions(-) diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd index a2af1a2..22e49fc 100644 --- a/lib/misc/async_port_wb.vhd +++ b/lib/misc/async_port_wb.vhd @@ -1,5 +1,5 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.14 2010-02-07 15:42:47 Jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -10,6 +10,7 @@ use work.async_types.all; entity async_port_wb is Generic ( + f_sysclk_hz : natural := 100E6; addr_width : natural := 32; data_width : natural := 32; byte_sel_width : natural := 4; @@ -72,9 +73,9 @@ architecture Behavioral of async_port_wb is ------------------------------------------------------------------ begin - ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure; - ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure; - ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure; + ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) > 0 report "Read pulse length must be greater than zero!" severity failure; + ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) > 0 report "Write pulse length must be greater than zero!" severity failure; + ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) > 1)) report "Read page pulse length must be greater than one!" severity failure; SRDY_O <= CYC_I and rdyo; en <= CYC_I and STB_I; @@ -110,7 +111,7 @@ architecture Behavioral of async_port_wb is process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read) begin - cycle_reload <= async_timespec.ncyc_pulse_rst; + cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk_hz); cc_rst <= '0'; as.rst <= '0'; as.cs <= '0'; @@ -138,17 +139,17 @@ architecture Behavioral of async_port_wb is if en = '1' then as.cs <= '1'; cc_rst <= '1'; - if async_timespec.ncyc_leadin = 0 then + if to_cycles(async_timespec.T_leadin, f_sysclk_hz) = 0 then sn <= pulse; if WE_I = '1' then cycle_reload <= 0; sn <= leadin; -- always lead-in for writes else - cycle_reload <= async_timespec.ncyc_pulse_rd-1; + cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1; as.rd <= '1'; end if; else - cycle_reload <= async_timespec.ncyc_leadin-1; + cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk_hz) - 1; sn <= leadin; end if; end if; @@ -162,9 +163,9 @@ architecture Behavioral of async_port_wb is cc_rst <= '1'; sn <= pulse; if WE_I_r = '1' then - cycle_reload <= async_timespec.ncyc_pulse_wr-1; + cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) - 1; else - cycle_reload <= async_timespec.ncyc_pulse_rd-1; + cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1; end if; end if; @@ -179,17 +180,17 @@ architecture Behavioral of async_port_wb is ack <= not WE_I_r; rdy <= do_page_read; if en = '1' and do_page_read = '1' then - cycle_reload <= async_timespec.ncyc_pulse_page_rd-1; + cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) - 1; sn <= pulse; - elsif async_timespec.ncyc_leadout = 0 then - if async_timespec.ncyc_release = 0 then + elsif to_cycles(async_timespec.T_leadout, f_sysclk_hz) = 0 then + if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then sn <= idle; else - cycle_reload <= async_timespec.ncyc_release-1; + cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1; sn <= release; end if; else - cycle_reload <= async_timespec.ncyc_leadout-1; + cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk_hz) - 1; sn <= leadout; end if; end if; @@ -199,10 +200,10 @@ architecture Behavioral of async_port_wb is as.drive_d <= WE_I_r; if cycle_cnt = 0 then cc_rst <= '1'; - if async_timespec.ncyc_release = 0 then + if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then sn <= idle; else - cycle_reload <= async_timespec.ncyc_release-1; + cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1; sn <= release; end if; end if; diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd index 295217f..f39a02a 100644 --- a/lib/misc/async_types.vhd +++ b/lib/misc/async_types.vhd @@ -28,15 +28,15 @@ USE IEEE.NUMERIC_STD.ALL; package async_types is type async_timespec_t is record - ncyc_leadin : natural; - ncyc_pulse_rd : natural; - ncyc_pulse_wr : natural; - ncyc_leadout : natural; - ncyc_release : natural; - ncyc_pulse_rst : natural; + T_leadin : real; + T_pulse_rd : real; + T_pulse_wr : real; + T_leadout : real; + T_release : real; + T_pulse_rst : real; + T_pulse_page_rd : real; can_page_rd : boolean; nbits_page_rd : natural; - ncyc_pulse_page_rd : natural; pol_cs : std_logic; pol_oe : std_logic; pol_we : std_logic; @@ -44,4 +44,16 @@ package async_types is pol_rst : std_logic; end record; + function to_cycles(T_ns : real; f_hz : natural) return natural; + +end async_types; + +package body async_types is + + function to_cycles(T_ns : real; f_hz : natural) return natural is + begin + + return natural(0.5 + 10.0E-9*T_ns*real(f_hz)); + + end to_cycles; end async_types; diff --git a/projects/mips_sys/src/async_defs_sim.vhd b/projects/mips_sys/src/async_defs_sim.vhd index 92c045a..8f58939 100644 --- a/projects/mips_sys/src/async_defs_sim.vhd +++ b/projects/mips_sys/src/async_defs_sim.vhd @@ -31,38 +31,38 @@ package async_defs is constant ts_flash : async_timespec_t := ( - ncyc_leadin => 1, - ncyc_pulse_rd => 12, - ncyc_pulse_wr => 7, - ncyc_leadout => 1, - ncyc_release => 4, - ncyc_pulse_rst => 8, - can_page_rd => true, - nbits_page_rd => 4, - ncyc_pulse_page_rd => 3, - pol_cs => '1', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' + T_leadin => 10.0, + T_pulse_rd => 120.0, + T_pulse_wr => 70.0, + T_leadout => 10.0, + T_release => 40.0, + T_pulse_rst => 80.0, + T_pulse_page_rd => 30.0, + can_page_rd => true, + nbits_page_rd => 4, + pol_cs => '1', + pol_oe => '0', + pol_we => '0', + pol_be => '0', + pol_rst => '0' ); constant ts_usb : async_timespec_t := ( - ncyc_leadin => 1, - ncyc_pulse_rd => 6, - ncyc_pulse_wr => 6, - ncyc_leadout => 1, - ncyc_release => 8, - ncyc_pulse_rst => 8, - can_page_rd => false, - nbits_page_rd => 0, - ncyc_pulse_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' + T_leadin => 10.0, + T_pulse_rd => 60.0, + T_pulse_wr => 60.0, + T_leadout => 10.0, + T_release => 80.0, + T_pulse_rst => 80.0, + T_pulse_page_rd => 00.0, + can_page_rd => false, + nbits_page_rd => 0, + pol_cs => '0', + pol_oe => '0', + pol_we => '0', + pol_be => '0', + pol_rst => '0' ); ---------------------------------------------------------------------------------------------- diff --git a/projects/mips_sys/src/sys_types.vhd b/projects/mips_sys/src/sys_types.vhd index 38da363..2ff4570 100644 --- a/projects/mips_sys/src/sys_types.vhd +++ b/projects/mips_sys/src/sys_types.vhd @@ -31,38 +31,38 @@ package async_defs is constant ts_flash : async_timespec_t := ( - ncyc_leadin => 0, - ncyc_pulse_rd => 12, - ncyc_pulse_wr => 7, - ncyc_leadout => 0, - ncyc_release => 4, - ncyc_pulse_rst => 8, - can_page_rd => true, - nbits_page_rd => 4, - ncyc_pulse_page_rd => 3, - pol_cs => '1', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' + T_leadin => 00.0, + T_pulse_rd => 120.0, + T_pulse_wr => 70.0, + T_leadout => 00.0, + T_release => 40.0, + T_pulse_rst => 80.0, + T_pulse_page_rd => 30.0, + can_page_rd => true, + nbits_page_rd => 4, + pol_cs => '1', + pol_oe => '0', + pol_we => '0', + pol_be => '0', + pol_rst => '0' ); constant ts_usb : async_timespec_t := ( - ncyc_leadin => 1, - ncyc_pulse_rd => 6, - ncyc_pulse_wr => 6, - ncyc_leadout => 1, - ncyc_release => 8, - ncyc_pulse_rst => 8, - can_page_rd => false, - nbits_page_rd => 0, - ncyc_pulse_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' + T_leadin => 10.0, + T_pulse_rd => 60.0, + T_pulse_wr => 60.0, + T_leadout => 10.0, + T_release => 80.0, + T_pulse_rst => 80.0, + T_pulse_page_rd => 00.0, + can_page_rd => false, + nbits_page_rd => 0, + pol_cs => '0', + pol_oe => '0', + pol_we => '0', + pol_be => '0', + pol_rst => '0' ); ----------------------------------------------------------------------------------------------