[Uart]

- uart_wb instantiates uart
- merged uart_tx, uart_rx into uart
- added uart implementations for Xilinx (kcuart) and Altera (JTAG)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1239 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/uart_jtag.vhd

@@ -0,0 +1,159 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
+LIBRARY work;
+use work.utils_pkg.all;
+
+------------------------------------------------------------------------------------
+ENTITY uart IS
+	Generic
+	(
+		FIFO_DEPTH_RX	: positive := 16;
+		FIFO_DEPTH_TX	: positive := 16
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		din			: in  unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic;
+		ctrl		: out ctrl_t;
+		status		: out status_t
+	);
+END uart;
+
+ARCHITECTURE jtag OF uart IS
+
+subtype addr_t is unsigned (2 downto 0);
+subtype reg_t is unsigned (7 downto 0);
+
+signal jtag_addr			: addr_t;
+signal jtag_din				: reg_t;
+signal jtag_dout			: reg_t;
+signal jtag_we				: STD_LOGIC;
+signal jtag_re				: STD_LOGIC;
+
+signal rx_fifo_dout			: reg_t;
+signal rx_fifo_full			: STD_LOGIC;
+signal rx_fifo_empty		: STD_LOGIC;
+
+signal tx_fifo_dout			: reg_t;
+signal tx_fifo_full			: STD_LOGIC;
+signal tx_fifo_empty		: STD_LOGIC;
+
+signal rx_data_cs			: STD_LOGIC;
+signal tx_data_cs			: STD_LOGIC;
+signal rx_data_we			: STD_LOGIC;
+signal tx_data_re			: STD_LOGIC;
+
+begin
+
+status.rx_present		<= not rx_fifo_empty;
+status.tx_complete		<= '1';
+status.tx_empty			<= tx_fifo_empty;
+status.tx_full			<= tx_fifo_full;
+	
+inst_jtag_reg:  entity work.jtag_reg
+	GENERIC MAP
+	(
+		INSTANCE_INDEX		=> 0,
+		DATA_WIDTH			=> reg_t'length,		-- bits
+		ADDR_WIDTH			=> addr_t'length		-- bits
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		addr_o				=> jtag_addr,
+		reg_i				=> jtag_din,
+		reg_o				=> jtag_dout,
+		we_o				=> jtag_we,
+		re_o				=> jtag_re
+	);
+
+rx_data_we	<= rx_data_cs and jtag_we;
+
+inst_rx_fifo: entity work.fifo_sync
+	Generic map
+	(
+		addr_width			=> NextExpBaseTwo(FIFO_DEPTH_RX),
+		data_width			=> reg_t'length
+	)
+	Port map
+	(
+		rst			=> rst,
+		clk			=> clk,
+		we			=> rx_data_we,
+		re			=> re,
+		fifo_full	=> rx_fifo_full,
+		fifo_empty	=> rx_fifo_empty,
+		data_w		=> jtag_dout,
+		data_r		=> dout
+	);
+
+tx_data_re	<= tx_data_cs and jtag_re;
+
+inst_tx_fifo: entity work.fifo_sync
+	Generic map
+	(
+		addr_width			=> NextExpBaseTwo(FIFO_DEPTH_TX),
+		data_width			=> reg_t'length
+	)
+	Port map
+	(
+		rst			=> rst,
+		clk			=> clk,
+		we			=> we,
+		re			=> tx_data_re,
+		fifo_full	=> tx_fifo_full,
+		fifo_empty	=> tx_fifo_empty,
+		data_w		=> din,
+		data_r		=> tx_fifo_dout
+	);
+
+-- JTAG Registers
+process(jtag_addr, tx_fifo_empty, rx_fifo_dout, tx_fifo_dout)
+begin
+	rx_data_cs	<= '0';
+	tx_data_cs	<= '0';
+	
+	jtag_din			<= "0000000" & tx_fifo_empty;
+	case jtag_addr is
+
+	-- Reg #0
+	when "000" => null;	-- Status
+
+	-- Reg #1
+	when "001" =>	-- RX-Data
+		rx_data_cs	<= '1';
+		jtag_din	<= rx_fifo_dout;
+
+	-- Reg #2
+	when "010" =>	-- TX-Data
+		tx_data_cs	<= '1';
+		jtag_din	<= tx_fifo_dout;
+		
+
+	when others => null;
+
+	end case;
+
+end process;		
+
+end jtag;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+

lib/uart/uart_rx.vhd

@@ -1,146 +0,0 @@
--- UART Receiver with integral 16 byte FIFO buffer
---
--- 8 bit, no parity, 1 stop bit
---
--- Version : 1.00
--- Version Date : 16th October 2002
---
--- Start of design entry : 16th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_RX
---
-entity uart_rx is
-    Port (            serial_in : in std_logic;
-                       data_out : out std_logic_vector(7 downto 0);
-                    read_buffer : in std_logic;
-                   reset_buffer : in std_logic;
-                   en_16_x_baud : in std_logic;
-            buffer_data_present : out std_logic;
-                    buffer_full : out std_logic;
-               buffer_half_full : out std_logic;
-                            clk : in std_logic);
-    end uart_rx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for UART_RX
---	 
-architecture macro_level_definition of uart_rx is
---
-------------------------------------------------------------------------------------
---
--- Components used in UART_RX and defined in subsequent entities.
---	
-------------------------------------------------------------------------------------
---
--- Constant (K) Compact UART Receiver
---
-component kcuart_rx 
-    Port (      serial_in : in std_logic;  
-                 data_out : out std_logic_vector(7 downto 0);
-              data_strobe : out std_logic;
-             en_16_x_baud : in std_logic;
-                      clk : in std_logic);
-    end component;
---
--- 'Bucket Brigade' FIFO 
---
-component bbfifo_16x8 
-    Port (       data_in : in std_logic_vector(7 downto 0);
-                data_out : out std_logic_vector(7 downto 0);
-                   reset : in std_logic;               
-                   write : in std_logic; 
-                    read : in std_logic;
-                    full : out std_logic;
-               half_full : out std_logic;
-            data_present : out std_logic;
-                     clk : in std_logic);
-    end component;
---
-------------------------------------------------------------------------------------
---
--- Signals used in UART_RX
---
-------------------------------------------------------------------------------------
---
-signal uart_data_out      : std_logic_vector(7 downto 0);
-signal fifo_write          : std_logic;
---
-------------------------------------------------------------------------------------
---
--- Start of UART_RX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  -- 8 to 1 multiplexer to convert parallel data to serial
-
-  kcuart: kcuart_rx
-  port map (     serial_in => serial_in,
-                  data_out => uart_data_out,
-               data_strobe => fifo_write,
-              en_16_x_baud => en_16_x_baud,
-                       clk => clk );
-
-
-  buf: bbfifo_16x8 
-  port map (       data_in => uart_data_out,
-                  data_out => data_out,
-                     reset => reset_buffer,              
-                     write => fifo_write,
-                      read => read_buffer,
-                      full => buffer_full,
-                 half_full => buffer_half_full,
-              data_present => buffer_data_present,
-                       clk => clk);
-
-end macro_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_RX.VHD
---
-------------------------------------------------------------------------------------
-
-

lib/uart/uart_rx_sim.vhd

@@ -1,55 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_RX
---
-entity uart_rx is
-    Port (            serial_in : in std_logic;
-                       data_out : out std_logic_vector(7 downto 0);
-                    read_buffer : in std_logic;
-                   reset_buffer : in std_logic;
-                   en_16_x_baud : in std_logic;
-            buffer_data_present : out std_logic;
-                    buffer_full : out std_logic;
-               buffer_half_full : out std_logic;
-                            clk : in std_logic);
-    end uart_rx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for UART_RX
---	 
-architecture behavior of uart_rx is
---
-------------------------------------------------------------------------------------
---
--- Signals used in UART_RX
---
-------------------------------------------------------------------------------------
---
---
-------------------------------------------------------------------------------------
---
--- Start of UART_RX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-data_out	        <= X"00";
-buffer_data_present	<= '0';
-buffer_full        	<= '0';
-buffer_half_full	<= '0';
-
-end behavior;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_RX.VHD
---
-------------------------------------------------------------------------------------
-
-

lib/uart/uart_sim.vhd

@@ -0,0 +1,64 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
+use std.textio.all; --  Imports the standard textio package.
+
+------------------------------------------------------------------------------------
+ENTITY uart IS
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		din			: in  unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic;
+		ctrl		: out ctrl_t;
+		status		: out status_t
+	);
+END uart;
+
+ARCHITECTURE simulation OF uart IS
+begin
+
+-- RX
+dout			        <= X"00";
+status.rx_present		<= '0';
+
+-- TX
+ser_tx 					<= '1';
+status.tx_complete		<= '1';
+status.tx_empty			<= '1';
+
+proc_tx: 
+	process(clk)
+	file output:	      text open write_mode is "STD_OUTPUT"; 
+	variable L : line; 
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				if din /= X"0D" then
+					write(L, character'val(to_integer(din)));
+				end if;	
+				if din = X"0A" then
+					writeline(output, L);
+				end if;
+			end if;	
+		end if;	
+	end process;
+
+end simulation;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+

lib/uart/uart_tx.vhd

@@ -1,153 +0,0 @@
--- UART Transmitter with integral 16 byte FIFO buffer
---
--- 8 bit, no parity, 1 stop bit
---
--- Version : 1.00
--- Version Date : 14th October 2002
---
--- Start of design entry : 14th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_TX
---
-entity uart_tx is
-    Port (            data_in : in std_logic_vector(7 downto 0);
-                 write_buffer : in std_logic;
-                 reset_buffer : in std_logic;
-                 en_16_x_baud : in std_logic;
-                   serial_out : out std_logic;
-                  buffer_full : out std_logic;
-             buffer_half_full : out std_logic;
-             tx_complete	  : out std_logic;
-             tx_empty		  : out std_logic;
-                          clk : in std_logic);
-    end uart_tx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for UART_TX
---	 
-architecture macro_level_definition of uart_tx is
---
-------------------------------------------------------------------------------------
---
--- Components used in UART_TX and defined in subsequent entities.
---	
-------------------------------------------------------------------------------------
---
--- Constant (K) Compact UART Transmitter
---
-component kcuart_tx 
-    Port (        data_in : in std_logic_vector(7 downto 0);
-           send_character : in std_logic;
-             en_16_x_baud : in std_logic;
-               serial_out : out std_logic;
-              Tx_complete : out std_logic;
-                      clk : in std_logic);
-    end component;
---
--- 'Bucket Brigade' FIFO 
---
-component bbfifo_16x8 
-    Port (       data_in : in std_logic_vector(7 downto 0);
-                data_out : out std_logic_vector(7 downto 0);
-                   reset : in std_logic;               
-                   write : in std_logic; 
-                    read : in std_logic;
-                    full : out std_logic;
-               half_full : out std_logic;
-            data_present : out std_logic;
-                     clk : in std_logic);
-    end component;
---
-------------------------------------------------------------------------------------
---
--- Signals used in UART_TX
---
-------------------------------------------------------------------------------------
---
-signal fifo_data_out      : std_logic_vector(7 downto 0);
-signal fifo_data_present  : std_logic;
-signal fifo_read          : std_logic;
---
-------------------------------------------------------------------------------------
---
--- Start of UART_TX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  tx_complete	<= fifo_read;
-  tx_empty		<= not fifo_data_present;
-  
-  -- 8 to 1 multiplexer to convert parallel data to serial
-
-  kcuart: kcuart_tx
-  port map (        data_in => fifo_data_out,
-             send_character => fifo_data_present,
-               en_16_x_baud => en_16_x_baud,
-                 serial_out => serial_out,
-                Tx_complete => fifo_read,
-                        clk => clk);
-
-
-  buf: bbfifo_16x8 
-  port map (       data_in => data_in,
-                  data_out => fifo_data_out,
-                     reset => reset_buffer,              
-                     write => write_buffer,
-                      read => fifo_read,
-                      full => buffer_full,
-                 half_full => buffer_half_full,
-              data_present => fifo_data_present,
-                       clk => clk);
-
-end macro_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_TX.VHD
---
-------------------------------------------------------------------------------------
-
-

lib/uart/uart_tx_sim.vhd

@@ -1,65 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; --  Imports the standard textio package.
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_TX
---
-entity uart_tx is
-    Port (            data_in : in std_logic_vector(7 downto 0);
-                 write_buffer : in std_logic;
-                 reset_buffer : in std_logic;
-                 en_16_x_baud : in std_logic;
-                   serial_out : out std_logic;
-                  buffer_full : out std_logic;
-             buffer_half_full : out std_logic;
-             tx_complete	  : out std_logic;
-             tx_empty		  : out std_logic;
-                          clk : in std_logic);
-    end uart_tx;
-
-------------------------------------------------------------------------------------
---
--- Start of UART_TX circuit description
---
-------------------------------------------------------------------------------------
---	
-
-ARCHITECTURE behavior OF uart_tx IS
-
-begin
-
-serial_out <= '0';
-buffer_full <= '0';
-buffer_half_full <= '0';
-tx_complete		<= '1';
-tx_empty		<= '1';
-
-registers_write: 
-	process(clk)
-	file output:	      text open write_mode is "STD_OUTPUT"; 
-	variable L : line; 
-	begin
-		if rising_edge(clk) then
-			if write_buffer = '1' then
-				if data_in /= X"0D" then
-					write(L, character'val(to_integer(unsigned(data_in))));
-				end if;	
-				if data_in = X"0A" then
-					writeline(output, L);
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-end behavior;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_TX.VHD
---
-------------------------------------------------------------------------------------
-
-

lib/uart/uart_types.vhd

@@ -0,0 +1,18 @@
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+package uart_types is
+
+	type ctrl_t is record
+		baudrate	: unsigned(15 downto 0);
+	end record;
+
+	type status_t is record
+		rx_present	: STD_LOGIC;
+		tx_complete	: STD_LOGIC;
+		tx_empty	: STD_LOGIC;
+		tx_full		: STD_LOGIC;
+	end record;
+	
+end uart_types;

lib/uart/uart_wb.vhd

@@ -2,6 +2,9 @@ LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
 ENTITY uart_wb IS
 	Port
 	(
@@ -23,65 +26,58 @@ ENTITY uart_wb IS
 	);
 END uart_wb;
 
-ARCHITECTURE behavior OF uart_wb IS
+ARCHITECTURE rtl OF uart_wb IS
 
-	COMPONENT uart_tx
+	COMPONENT uart
-    Port
-    (
-		data_in				: in std_logic_vector(7 downto 0);
-		write_buffer		: in std_logic;
-		reset_buffer		: in std_logic;
-		en_16_x_baud		: in std_logic;
-		serial_out			: out std_logic;
-		buffer_full			: out std_logic;
-		buffer_half_full	: out std_logic;
-		tx_complete			: out std_logic;
-		tx_empty			: out std_logic;
-		clk					: in std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT uart_rx
 	Port
 	(
-		serial_in			: in std_logic;
+		clk			: in  STD_LOGIC;
-		data_out			: out std_logic_vector(7 downto 0);
+		rst			: in  STD_LOGIC;
-		read_buffer			: in std_logic;
+		we			: in  STD_LOGIC;
-		reset_buffer		: in std_logic;
+		re			: in  STD_LOGIC;
-		en_16_x_baud		: in std_logic;
+		din			: in  unsigned(7 downto 0);
-		buffer_data_present	: out std_logic;
+		dout		: out unsigned(7 downto 0);
-		buffer_full			: out std_logic;
+		ser_rx		: in std_logic;
-		buffer_half_full	: out std_logic;
+		ser_tx		: out std_logic;
-		clk					: in std_logic
+		ctrl		: out ctrl_t;
+		status		: out status_t
 	);
 	END COMPONENT;
 	
 	-- Signals for UART connections
-	signal baud_count		: unsigned(15 downto 0);
+	signal reg_uart_baud	: unsigned(15 downto 0);
-	signal en_16_x_baud		: std_logic;
 	signal reg_we_uart_tx	: std_logic;
-	signal tx_full			: std_logic;
-	signal tx_half_full		: std_logic;
 	signal reg_re_uart_rx	: std_logic;
 	signal reg_uart_tx		: unsigned(7 downto 0);
-	signal reg_uart_rx		: std_logic_vector(7 downto 0);
+	signal reg_uart_rx		: unsigned(7 downto 0);
-	signal rx_data_present	: std_logic;
-	signal rx_full			: std_logic;
-	signal rx_half_full		: std_logic;
 	signal uart_status_port	: unsigned(15 downto 0);
-	signal reg_uart_baud	: unsigned(15 downto 0);
 	signal rx_int_en		: std_logic;
 	signal tx_int_en		: std_logic;
 	signal irq_rx			: std_logic;
 	signal irq_tx			: std_logic;
-	signal tx_complete		: std_logic;
+	
-	signal tx_empty			: std_logic;
+	signal ctrl				: ctrl_t;
-	signal status_real		: unsigned(15 downto 0);
+	signal status			: status_t;
-	signal status_sim		: unsigned(15 downto 0);
 	
 begin
 
-	SRDY_O	<= CYC_I;
+	SRDY_O			<= CYC_I;
+	ctrl.baudrate	<= reg_uart_baud;
+	
+inst_uart : uart
+	PORT MAP
+	(
+		clk			=> CLK_I,
+		rst			=> RST_I,
+		we			=> reg_we_uart_tx,
+		re			=> reg_re_uart_rx,
+		din			=> reg_uart_tx,
+		dout		=> reg_uart_rx,
+		ser_rx		=> ser_rx,
+		ser_tx		=> ser_tx,
+		ctrl		=> ctrl,
+		status		=> status
+	);
 	
 ------------------------------------------------------------------
 registers_write: 
@@ -126,7 +122,7 @@ registers_read:
 
 				when "0000" =>
 					reg_re_uart_rx		<= not WE_I;
-					DAT_O(7 downto 0)	<= unsigned(reg_uart_rx);
+					DAT_O(7 downto 0)	<= reg_uart_rx;
 
 				when "0001" =>
 					DAT_O(15 downto 0)	<= uart_status_port;
@@ -140,62 +136,17 @@ registers_read:
 		end if;	
 	end process;
 
-baud_timer:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				baud_count <= (others => '0');
-			elsif baud_count = reg_uart_baud then
-				baud_count <= (others => '0');
-				en_16_x_baud <= '1';
-			else
-				baud_count <= baud_count + 1;
-				en_16_x_baud <= '0';
-			end if;
-		end if;
-	end process;
-
 irq_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			irq_tx		<= tx_empty and tx_int_en;
+			irq_tx		<= status.tx_empty and tx_int_en;
-			irq_rx		<= rx_data_present and rx_int_en;
+			irq_rx		<= status.rx_present and rx_int_en;
 		end if;
 	end process;
 	
-inst_uart_tx: entity work.uart_tx 
+	uart_status_port		<= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & status.rx_present & '0' & '0' & status.tx_full & '0' ;
-	port map
-	(
-		data_in				=> std_logic_vector(reg_uart_tx), 
-		write_buffer		=> reg_we_uart_tx,
-		reset_buffer		=> RST_I,
-		en_16_x_baud		=> en_16_x_baud,
-		serial_out			=> ser_tx,
-		buffer_full			=> tx_full,
-		buffer_half_full	=> tx_half_full,
-		tx_complete			=> tx_complete,
-		tx_empty			=> tx_empty,
-		clk					=> CLK_I
-	);
-	
-inst_uart_rx: entity work.uart_rx
-	port map
-	(
-		serial_in			=> ser_rx,
-		data_out			=> reg_uart_rx,
-		read_buffer			=> reg_re_uart_rx,
-		reset_buffer		=> RST_I,
-		en_16_x_baud		=> en_16_x_baud,
-		buffer_data_present => rx_data_present,
-		buffer_full			=> rx_full,
-		buffer_half_full	=> rx_half_full,
-		clk					=> CLK_I
-	);  
-	
-	uart_status_port		<= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
 	
 	INT_O				<= irq_rx or irq_tx;
 
-end behavior;
+end rtl;

lib/uart/uart_xil.vhd

@@ -0,0 +1,100 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
+------------------------------------------------------------------------------------
+ENTITY uart IS
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		din			: in  unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic;
+		ctrl		: out ctrl_t;
+		status		: out status_t
+	);
+END uart;
+
+ARCHITECTURE rtl OF uart IS
+
+signal baud_count		: unsigned(15 downto 0);
+signal en_16_x_baud		: std_logic;
+
+signal rx_data_present	: std_logic;
+signal rx_full			: std_logic;
+signal rx_half_full		: std_logic;
+
+signal tx_complete		: std_logic;
+signal tx_empty			: std_logic;
+signal tx_full			: std_logic;
+signal tx_half_full		: std_logic;
+
+begin
+
+baud_timer:
+process(clk)
+begin
+	if rising_edge(CLK_I) then
+		if rst = '1' then
+			baud_count <= (others => '0');
+		elsif baud_count = ctrl.baudrate then
+			baud_count <= (others => '0');
+			en_16_x_baud <= '1';
+		else
+			baud_count <= baud_count + 1;
+			en_16_x_baud <= '0';
+		end if;
+	end if;
+end process;
+
+inst_uart_tx: entity work.uart_tx 
+	port map
+	(
+		data_in				=> std_logic_vector(din), 
+		write_buffer		=> we,
+		reset_buffer		=> rst,
+		en_16_x_baud		=> en_16_x_baud,
+		serial_out			=> ser_tx,
+		buffer_full			=> tx_full,
+		buffer_half_full	=> tx_half_full,
+		tx_complete			=> tx_complete,
+		tx_empty			=> tx_empty,
+		clk					=> clk
+	);
+	
+inst_uart_rx: entity work.uart_rx
+	port map
+	(
+		serial_in			=> ser_rx,
+		unsigned(data_out)	=> dout,
+		read_buffer			=> re,
+		reset_buffer		=> rst,
+		en_16_x_baud		=> en_16_x_baud,
+		buffer_data_present => rx_data_present,
+		buffer_full			=> rx_full,
+		buffer_half_full	=> rx_half_full,
+		clk					=> clk
+	);  
+
+-- Status
+status.rx_present		<= rx_data_present;
+status.tx_complete		<= tx_complete;
+status.tx_empty			<= tx_empty;
+status.tx_full			<= tx_full;
+
+end rtl;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+