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[Uart]

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- uart_wb instantiates uart
- merged uart_tx, uart_rx into uart
- added uart implementations for Xilinx (kcuart) and Altera (JTAG)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1239 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-27 15:50:32 +00:00
parent 4d598154ca
commit 11fa96a4e7
9 changed files with 385 additions and 512 deletions
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lib/uart/uart_wb.vhd
+44 -93
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@@ -2,6 +2,9 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
ENTITY uart_wb IS
Port
(
@@ -23,65 +26,58 @@ ENTITY uart_wb IS
);
END uart_wb;
ARCHITECTURE behavior OF uart_wb IS
ARCHITECTURE rtl OF uart_wb IS
COMPONENT uart_tx
Port
(
data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
tx_complete : out std_logic;
tx_empty : out std_logic;
clk : in std_logic
);
END COMPONENT;
COMPONENT uart_rx
Port
COMPONENT uart
Port
(
serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : out ctrl_t;
status : out status_t
);
END COMPONENT;
-- Signals for UART connections
signal baud_count : unsigned(15 downto 0);
signal en_16_x_baud : std_logic;
signal reg_uart_baud : unsigned(15 downto 0);
signal reg_we_uart_tx : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal reg_re_uart_rx : std_logic;
signal reg_uart_tx : unsigned(7 downto 0);
signal reg_uart_rx : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal reg_uart_rx : unsigned(7 downto 0);
signal uart_status_port : unsigned(15 downto 0);
signal reg_uart_baud : unsigned(15 downto 0);
signal rx_int_en : std_logic;
signal tx_int_en : std_logic;
signal irq_rx : std_logic;
signal irq_tx : std_logic;
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal status_real : unsigned(15 downto 0);
signal status_sim : unsigned(15 downto 0);
signal ctrl : ctrl_t;
signal status : status_t;
begin
SRDY_O <= CYC_I;
SRDY_O <= CYC_I;
ctrl.baudrate <= reg_uart_baud;
inst_uart : uart
PORT MAP
(
clk => CLK_I,
rst => RST_I,
we => reg_we_uart_tx,
re => reg_re_uart_rx,
din => reg_uart_tx,
dout => reg_uart_rx,
ser_rx => ser_rx,
ser_tx => ser_tx,
ctrl => ctrl,
status => status
);
------------------------------------------------------------------
registers_write:
@@ -126,7 +122,7 @@ registers_read:
when "0000" =>
reg_re_uart_rx <= not WE_I;
DAT_O(7 downto 0) <= unsigned(reg_uart_rx);
DAT_O(7 downto 0) <= reg_uart_rx;
when "0001" =>
DAT_O(15 downto 0) <= uart_status_port;
@@ -140,62 +136,17 @@ registers_read:
end if;
end process;
baud_timer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
baud_count <= (others => '0');
elsif baud_count = reg_uart_baud then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process;
irq_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
irq_tx <= tx_empty and tx_int_en;
irq_rx <= rx_data_present and rx_int_en;
irq_tx <= status.tx_empty and tx_int_en;
irq_rx <= status.rx_present and rx_int_en;
end if;
end process;
inst_uart_tx: entity work.uart_tx
port map
(
data_in => std_logic_vector(reg_uart_tx),
write_buffer => reg_we_uart_tx,
reset_buffer => RST_I,
en_16_x_baud => en_16_x_baud,
serial_out => ser_tx,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
tx_complete => tx_complete,
tx_empty => tx_empty,
clk => CLK_I
);
inst_uart_rx: entity work.uart_rx
port map
(
serial_in => ser_rx,
data_out => reg_uart_rx,
read_buffer => reg_re_uart_rx,
reset_buffer => RST_I,
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => CLK_I
);
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & status.rx_present & '0' & '0' & status.tx_full & '0' ;
INT_O <= irq_rx or irq_tx;
end behavior;
end rtl;