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- using fir_stage_sys instead of fir_stage

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git-svn-id: http://moon:8086/svn/vhdl/trunk@189 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-02 16:23:04 +00:00
parent eb818a15bb
commit 0ed3e397f2
1 changed files with 7 additions and 42 deletions
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lib/filter/src/fir_iterative.vhd
+7 -42
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@@ -54,7 +54,7 @@ Port
srst : in std_logic; srst : in std_logic;
clk : in std_logic; clk : in std_logic;
h_din : in sfixed; h_din : in sfixed;
h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); h_addr_out : out natural;
ready : out std_logic; ready : out std_logic;
x_valid : in std_logic; x_valid : in std_logic;
x_din : in sfixed; x_din : in sfixed;
@@ -65,36 +65,6 @@ end fir_iterative;
architecture Behavioral of fir_iterative is architecture Behavioral of fir_iterative is
-------------------------------------------------------------------------------
-- Component Declaration for FIR stage
COMPONENT fir_stage
GENERIC
(
nbits_in : integer;
nbits_in_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
has_in_reg : boolean;
has_pipe_reg : boolean;
fir_mode : fir_stage_mode_t;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
in_valid : in std_logic;
x_in : in sfixed;
y_in : in sfixed;
h_in : in sfixed;
out_valid : out std_logic;
x_out : out sfixed;
y_out : out sfixed;
y_out_clr : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
constant fir_stage_mode : fir_stage_mode_t := transposed; constant fir_stage_mode : fir_stage_mode_t := transposed;
constant ntaps_is_even : boolean := (ntaps mod 2) = 0; constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
@@ -127,7 +97,7 @@ architecture Behavioral of fir_iterative is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
begin begin
h_addr_out <= to_unsigned(h_addr, h_addr_bits); h_addr_out <= h_addr;
x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate); x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate);
---------------------------------------- ----------------------------------------
@@ -325,30 +295,25 @@ begin
end process; end process;
---------------------------------------- ----------------------------------------
inst_fir_stage: fir_stage inst_fir_stage: entity work.fir_stage_sys
GENERIC MAP GENERIC MAP
( (
nbits_in => nbits_stages, nbits_in => nbits_stages,
nbits_in_frac => nbits_stages_frac, nbits_in_frac => nbits_stages_frac,
nbits_out => nbits_stages, nbits_out => nbits_stages,
nbits_out_frac => nbits_stages_frac, nbits_out_frac => nbits_stages_frac,
has_in_reg => true, input_latency => 1,
has_pipe_reg => true, coef_latency => 1,
fir_mode => fir_stage_mode, pipe_latency => 3
rounding => false,
saturating => false
) )
PORT MAP PORT MAP
( (
srst => srst, rst => fir_stage_clr,
clk => clk, clk => clk,
in_valid => fir_stage_en,
x_in => x_stage, x_in => x_stage,
y_in => y_stage, y_in => y_stage,
h_in => h_din, h_in => h_din,
out_valid => stage_valid,
x_out => xo, x_out => xo,
y_out_clr => fir_stage_clr,
y_out => y_stage y_out => y_stage
); );