From 0ed3e397f246568d7143ee1bb7419784d7546e86 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 2 Jan 2009 16:23:04 +0000 Subject: [PATCH] - using fir_stage_sys instead of fir_stage git-svn-id: http://moon:8086/svn/vhdl/trunk@189 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/fir_iterative.vhd | 49 +++++--------------------------- 1 file changed, 7 insertions(+), 42 deletions(-) diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd index 2526e67..647b1ae 100644 --- a/lib/filter/src/fir_iterative.vhd +++ b/lib/filter/src/fir_iterative.vhd @@ -54,7 +54,7 @@ Port srst : in std_logic; clk : in std_logic; h_din : in sfixed; - h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); + h_addr_out : out natural; ready : out std_logic; x_valid : in std_logic; x_din : in sfixed; @@ -66,36 +66,6 @@ end fir_iterative; architecture Behavioral of fir_iterative is ------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic - ); - END COMPONENT; - - ------------------------------------------------------------------------------- constant fir_stage_mode : fir_stage_mode_t := transposed; constant ntaps_is_even : boolean := (ntaps mod 2) = 0; constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode); @@ -127,7 +97,7 @@ architecture Behavioral of fir_iterative is ------------------------------------------------------------------------------- begin - h_addr_out <= to_unsigned(h_addr, h_addr_bits); + h_addr_out <= h_addr; x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate); ---------------------------------------- @@ -325,30 +295,25 @@ begin end process; ---------------------------------------- - inst_fir_stage: fir_stage + inst_fir_stage: entity work.fir_stage_sys GENERIC MAP ( nbits_in => nbits_stages, nbits_in_frac => nbits_stages_frac, nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, - has_in_reg => true, - has_pipe_reg => true, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false + input_latency => 1, + coef_latency => 1, + pipe_latency => 3 ) PORT MAP ( - srst => srst, + rst => fir_stage_clr, clk => clk, - in_valid => fir_stage_en, x_in => x_stage, y_in => y_stage, h_in => h_din, - out_valid => stage_valid, x_out => xo, - y_out_clr => fir_stage_clr, y_out => y_stage );