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- use async_be

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git-svn-id: http://moon:8086/svn/vhdl/trunk@326 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-08 17:34:55 +00:00
parent 5226b0bb0a
commit 0e825a1df5
5 changed files with 72 additions and 40 deletions
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projects/mips_sys/src/mips_sys.vhd
+6 -7
View File
@@ -218,8 +218,9 @@ ARCHITECTURE behavior OF mips_sys IS
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out unsigned(byte_sel_width-1 downto 0);
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
@@ -331,8 +332,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
signal usb_wrn : unsigned(0 downto 0);
signal flash_wrn : unsigned(0 downto 0);
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -461,8 +460,6 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_usb_wrn <= usb_wrn(0);
sys_flash_wrn <= flash_wrn(0);
---------------------------------------------------------------
-- Arbiter
@@ -717,8 +714,9 @@ inst_flash_port : async_port_wb
async_a => sys_flash_a,
async_d => sys_flash_d,
async_cs => sys_flash_ce,
async_wr => flash_wrn,
async_wr => sys_flash_wrn,
async_rd => sys_flash_rdn,
async_be => open,
async_rst => flash_rstn
);
@@ -747,8 +745,9 @@ inst_usb_port : async_port_wb
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
async_wr => usb_wrn,
async_wr => sys_usb_wrn,
async_rd => sys_usb_rdn,
async_be => open,
async_rst => open
);
projects/mips_sys/src/mips_sys_sim.vhd
+4 -4
View File
@@ -228,8 +228,9 @@ ARCHITECTURE behavior OF mips_sys IS
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out unsigned(byte_sel_width-1 downto 0);
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
@@ -388,7 +389,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_we_n : std_logic;
signal flash_d_drv : std_logic;
signal flash_bsy : std_logic;
signal usb_wrn : unsigned(0 downto 0);
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -515,7 +515,6 @@ BEGIN
rst_in <= not sys_rst_n_in;
rst <= not locked;
sys_usb_rstn <= not gpo1(0);
sys_usb_wrn <= usb_wrn(0);
sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0';
@@ -844,8 +843,9 @@ inst_usb_port : async_port_wb
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
async_wr => usb_wrn,
async_wr => sys_usb_wrn,
async_rd => sys_usb_rdn,
async_be => open,
async_rst => open
);
projects/mips_sys/src/sys_types.vhd
+2
View File
@@ -40,6 +40,7 @@ package async_defs is
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
@@ -54,6 +55,7 @@ package async_defs is
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);