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- changed frequencies into MHz units (real data type)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@734 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 07:50:27 +00:00
parent 385aa5e008
commit 0c50e933f8
19 changed files with 161 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/clockgen_virtex4.vhd
+11 -11
View File
@@ -33,9 +33,9 @@ use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq_hz : integer := 100E6;
vga_clk_out_freq_hz : integer := 100E6;
sys_clk_out_freq_hz : integer := 100E6;
clk_in_freq : real := 100.0;
vga_clk_out_freq : real := 100.0;
sys_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
);
@@ -93,10 +93,10 @@ begin
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
@@ -146,10 +146,10 @@ BUFG_vga_clkfx : BUFG
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, sys_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, sys_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
@@ -204,7 +204,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -256,7 +256,7 @@ bufg_sdr0_clk270: bufg
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
projects/mips_sys/src/mips_sys.vhd
+26 -17
View File
@@ -42,10 +42,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 100E6;
ddr_frequency_hz : integer := 100E6;
ddr_phaseshift : integer := 0;
sys_freq_in : real := 100.0;
sys_freq : real := 125.0;
sdram_freq : real := 125.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
@@ -195,10 +195,10 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
@@ -248,6 +248,10 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := 100.0
);
PORT
(
CLK_I : in STD_LOGIC;
@@ -464,6 +468,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
@@ -723,6 +728,10 @@ inst_lcd_port: lcd_port
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
@@ -748,7 +757,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -781,7 +790,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -855,9 +864,9 @@ inst_uart_wb_1 : uart_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
@@ -881,8 +890,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => sys_freq,
f_sdrclk_hz => ddr_frequency_hz,
f_sysclk => sys_freq,
f_sdrclk => sdram_freq,
fifo_depth => 5
)
PORT MAP
@@ -1004,7 +1013,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(
@@ -1043,7 +1052,7 @@ inst_ps2_phy_0: entity work.ps2_phy
inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(
projects/mips_sys/src/mips_sys_sim.vhd
+29 -21
View File
@@ -43,10 +43,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 125E6;
ddr_frequency_hz : integer := 125E6;
ddr_phaseshift : integer := 0;
sys_freq_in : real := 100.0;
sys_freq : real := 125.0;
sdram_freq : real := 125.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
@@ -201,10 +201,10 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
@@ -235,9 +235,9 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT flash_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
PORT
@@ -288,6 +288,10 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := 100.0
);
PORT
(
CLK_I : in STD_LOGIC;
@@ -516,8 +520,8 @@ ARCHITECTURE behavior OF mips_sys IS
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant topad : time := 3 ns;
constant topad : time := 3 ns;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
@@ -785,6 +789,10 @@ inst_lcd_port: lcd_port
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
@@ -810,7 +818,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : flash_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
async_timespec => ts_flash
@@ -843,7 +851,7 @@ inst_flash_port : flash_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 2,
data_width => 16,
byte_sel_width => 1,
@@ -978,9 +986,9 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
@@ -1005,8 +1013,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => sys_freq,
f_sdrclk_hz => ddr_frequency_hz,
f_sysclk => sys_freq,
f_sdrclk => sdram_freq,
fifo_depth => 5
)
PORT MAP
@@ -1127,7 +1135,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(