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- changed frequencies into MHz units (real data type)

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Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@734 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 07:50:27 +00:00
parent 385aa5e008
commit 0c50e933f8
19 changed files with 161 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+7 -7
View File
@@ -31,8 +31,8 @@ use work.sdram_types.all;
entity sdram_cmd is
Generic
(
f_sdrclk_hz : natural := 100E6;
BL : natural := 2
f_sdrclk : real := 100.0;
BL : natural := 2
);
Port
(
@@ -73,13 +73,13 @@ architecture behaviour of sdram_cmd is
( SD_DESELECT => (0 ),
SD_NOP => (0 ),
SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk_hz)-1),
SD_ACT => (to_cycles(TRCD, f_sdrclk)-1),
SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk_hz)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk_hz)-1),
SD_WRITE => (to_cycles(TWR, f_sdrclk)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk)-1),
SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk_hz)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk_hz)-1)
SD_AR => (to_cycles(TRFC, f_sdrclk)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk)-1)
);
begin
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+4 -4
View File
@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk_hz : natural := 100E6;
BL : natural := 2
f_sysclk : real := 100.0;
BL : natural := 2
);
Port (
rst : in STD_LOGIC;
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk_hz);
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk_hz);
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+6 -6
View File
@@ -32,10 +32,10 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
fifo_depth : integer := 4
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : integer := 4
);
Port
(
@@ -205,8 +205,8 @@ begin
Generic map
(
BL => BL,
f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+5 -5
View File
@@ -32,9 +32,9 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : integer := 4
);
Port
@@ -205,8 +205,8 @@ begin
Generic map
(
BL => BL,
f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+5 -5
View File
@@ -31,9 +31,9 @@ use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : natural := 3
);
Port
@@ -133,7 +133,7 @@ begin
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
f_sysclk_hz => f_sysclk_hz,
f_sysclk => f_sysclk,
BL => BL
)
Port map
@@ -180,7 +180,7 @@ begin
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
f_sdrclk_hz => f_sdrclk_hz,
f_sdrclk => f_sdrclk,
BL => BL
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+3 -3
View File
@@ -113,16 +113,16 @@ package sdram_types is
wait_cycle : natural;
end record init_seq_t;
function to_cycles(T_ns : real; f_hz : natural) return natural;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end sdram_types;
package body sdram_types is
function to_cycles(T_ns : real; f_hz : natural) return natural is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
return natural(0.5 + 1.0E-3*T_ns*f_Mhz);
end to_cycles;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+3 -3
View File
@@ -122,7 +122,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk_in_freq => 100.0,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -151,8 +151,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => 100E6,
f_sdrclk_hz => 133E6,
f_sysclk => 100.000,
f_sdrclk => 133.333,
fifo_depth => 4
)
PORT MAP
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+3 -3
View File
@@ -119,7 +119,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk_in_freq => 100.0,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -146,8 +146,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => 100E6,
f_sdrclk_hz => 100E6,
f_sysclk => 100.0,
f_sdrclk => 100.0,
fifo_depth => 4
)
PORT MAP