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git-svn-id: http://moon:8086/svn/vhdl/trunk@1097 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-05-16 17:41:08 +00:00
parent f6e00c3922
commit 0afb7b1758
15 changed files with 120463 additions and 0 deletions
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Common/sim/altera/libsrc/altera/alt_cusp_package.vhd
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PACKAGE ALT_CUSP_PACKAGE IS
END ALT_CUSP_PACKAGE;
Common/sim/altera/libsrc/altera/alt_dspbuilder_package.vhd
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Common/sim/altera/libsrc/altera/altera_europa_support_lib.vhd
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- --
-- Description: Declares utility package for Altera IP support --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
package altera_europa_support_lib is
attribute IS_SIGNED : BOOLEAN ;
attribute SYNTHESIS_RETURN : STRING ;
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION A_SRL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SRL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR) return Std_Logic;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC;
-- Result subtype: STD_LOGIC
-- Result: Converts a BOOLEAN to a STD_LOGIC..
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
function a_min(L, R: INTEGER) return INTEGER ;
function a_max(L, R: INTEGER) return INTEGER ;
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
-- All required padding is to the left of the value (right justified) to
-- a string that can hold the maximum value of the vector in that radix.
-- When displaying decimal values (e.g. %d), padding is spaces.
-- When displaying other radices (e.g. %h), padding is zeros.
-- There is no padding when a zero is placed after the % (e.g. %0d or %0h).
type pad_type is (pad_none, pad_spaces, pad_zeros);
function to_hex_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : integer;
pad : pad_type := pad_spaces) return string;
function to_decimal_string(val : std_logic_vector;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_hex_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : std_logic;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
end altera_europa_support_lib;
package body altera_europa_support_lib is
--
-- Reducing logical functions.
--
FUNCTION and_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION or_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result OR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NOR" ;
BEGIN
result := NOT or_reduce(arg);
RETURN result;
END;
FUNCTION xor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result XOR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION xnor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_XNOR" ;
BEGIN
result := NOT xor_reduce(arg);
RETURN result;
END;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC is
begin
if(arg = true) then
return('1');
else
return('0');
end if;
end;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SRL(arg,conv_integer(shift)));
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SLL(arg,conv_integer(shift)));
END;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT - shift DOWNTO 0) := arg(arg'LEFT DOWNTO shift);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT DOWNTO shift) := arg(arg'LEFT - shift DOWNTO 0);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector IS
BEGIN
IF a = '1' THEN
return "1";
ELSE
return "0";
END IF;
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector IS
BEGIN
return a;
END;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR)
return Std_Logic IS
BEGIN
return (vector(vector'right));
END;
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(repeat-1 DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result(i) := arg;
end LOOP;
RETURN(result);
END;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR(((repeat * (arg_copy'LEFT+1))-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result((((arg_copy'left + 1) * i) + arg_copy'left) downto ((arg_copy'left + 1) * i)) := arg_copy(arg_copy'LEFT DOWNTO 0);
end LOOP;
RETURN(result);
END;
-- a_min : return the minimum of two integers;
function a_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- a_max : return the minimum of two integers;
function a_max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
-- a_ext is the Altera version of the EXT function. It is used to both
-- zero-extend a signal to a new length, and to extract a signal of 'size'
-- length from a larger signal.
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
VARIABLE bits_to_copy : integer := 0;
VARIABLE arg_length : integer := arg'length ;
VARIABLE LSB_bit : integer := 0;
BEGIN
bits_to_copy := a_min(arg_length, size);
FOR i IN 0 TO (bits_to_copy - 1) LOOP
result(i) := arg_copy(i);
end LOOP;
RETURN(result);
END;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
subtype slv4 is std_logic_vector(1 to 4);
subtype slv3 is std_logic_vector(1 to 3);
-- Remove leading zeros. Also changes strings of all 'x' or 'z' to one char.
-- This handles the %0<radix> kind of Verilog syntax in the format string.
-- Examples:
-- input output
-- ----- -----------
-- 001f 1f
-- 0000 0
-- xxxx x
-- zzzz z
-- xxzz xxzz
function do_pad_none(
str_in : string) return string is
variable start : integer;
variable all_x : boolean := true;
variable all_z : boolean := true;
begin
-- Nothing to remove if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
case str_in(i) is
when 'X' | 'x' => all_z := false;
when 'Z' | 'z' => all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x or all_z) then
return str_in(str_in'left to str_in'left);
end if;
-- Find index of first non-zero character.
for i in str_in'range loop
start := i;
exit when (str_in(i) /= '0');
end loop;
return str_in(start to str_in'right);
end do_pad_none;
-- Replace leading zeros with spaces.
-- This handles the %d kind of Verilog syntax in the format string.
function replace_leading_zeros(
str_in : string;
c : character) return string is
variable str_out : string(str_in'range) := str_in;
begin
-- Nothing to replace if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
if (str_in(i) = '0') then
str_out(i) := c;
else
exit;
end if;
end loop;
return str_out;
end replace_leading_zeros;
function do_pad(
str : string;
pad : pad_type) return string is
begin
case pad is
when pad_none => return do_pad_none(str);
when pad_spaces => return replace_leading_zeros(str, ' ');
when pad_zeros => return str;
end case;
end do_pad;
function round_up_to_multiple(
val : integer;
size : integer) return integer is
begin
return ((val + size - 1) / size) * size;
end round_up_to_multiple;
function to_hex_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,4);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/4)+1 := 1;
variable str : string(1 to ext_len/4) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 4 /= 1;
case slv4(to_x01z(val_ext(i to i+3))) is
when "0000" => str(ptr) := '0';
when "0001" => str(ptr) := '1';
when "0010" => str(ptr) := '2';
when "0011" => str(ptr) := '3';
when "0100" => str(ptr) := '4';
when "0101" => str(ptr) := '5';
when "0110" => str(ptr) := '6';
when "0111" => str(ptr) := '7';
when "1000" => str(ptr) := '8';
when "1001" => str(ptr) := '9';
when "1010" => str(ptr) := 'a';
when "1011" => str(ptr) := 'b';
when "1100" => str(ptr) := 'c';
when "1101" => str(ptr) := 'd';
when "1110" => str(ptr) := 'e';
when "1111" => str(ptr) := 'f';
when "XXXX" => str(ptr) := 'x';
when "ZZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 3 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_hex_string;
function to_decimal_string(
val : integer;
pad : pad_type := pad_spaces) return string is
variable tmp : integer := val;
variable ptr : integer range 1 to 32 := 32;
variable str : string(1 to 32) := (others=>'0');
begin
if val=0 then
return do_pad("0", pad);
else
while tmp > 0 loop
case tmp rem 10 is
when 0 => str(ptr) := '0';
when 1 => str(ptr) := '1';
when 2 => str(ptr) := '2';
when 3 => str(ptr) := '3';
when 4 => str(ptr) := '4';
when 5 => str(ptr) := '5';
when 6 => str(ptr) := '6';
when 7 => str(ptr) := '7';
when 8 => str(ptr) := '8';
when 9 => str(ptr) := '9';
when others => null;
end case;
tmp := tmp / 10;
ptr := ptr - 1;
end loop;
return do_pad(str(ptr+1 to 32), pad);
end if;
end to_decimal_string;
function to_decimal_string(
val : std_logic_vector;
pad : pad_type := pad_spaces) return string is
variable all_x : boolean := true;
variable all_z : boolean := true;
variable some_x : boolean := false;
variable some_z : boolean := false;
variable fixed_str : string(1 to 1);
begin
for i in val'range loop
case to_x01z(val(i)) is
when 'X' => some_x := true; all_z := false;
when 'Z' => some_z := true; all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x) then
fixed_str(1) := 'x';
return fixed_str;
elsif (all_z) then
fixed_str(1) := 'z';
return fixed_str;
elsif (some_x) then
fixed_str(1) := 'X';
return fixed_str;
elsif (some_z) then
fixed_str(1) := 'Z';
return fixed_str;
else
return to_decimal_string(conv_integer(val), pad);
end if;
end to_decimal_string;
function to_octal_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,3);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/3)+1 := 1;
variable str : string(1 to ext_len/3) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 3 /= 1;
case slv3(to_x01z(val_ext(i to i+2))) is
when "000" => str(ptr) := '0';
when "001" => str(ptr) := '1';
when "010" => str(ptr) := '2';
when "011" => str(ptr) := '3';
when "100" => str(ptr) := '4';
when "101" => str(ptr) := '5';
when "110" => str(ptr) := '6';
when "111" => str(ptr) := '7';
when "XXX" => str(ptr) := 'x';
when "ZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 2 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_octal_string;
function to_hex_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_hex_string;
function to_decimal_string(
val : std_logic;
pad : pad_type := pad_spaces) return string is
begin
return to_binary_string(val, pad);
end to_decimal_string;
function to_octal_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_octal_string;
function to_binary_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to 1);
begin
case to_x01z(val) is
when '0' => str(1) := '0';
when '1' => str(1) := '1';
when 'X' => str(1) := 'x';
when 'Z' => str(1) := 'z';
when others => str(1) := 'x';
end case;
return do_pad(str, pad);
end to_binary_string;
function to_binary_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to val'length) := (others=>'0');
variable ptr : integer := str'left;
begin
for i in val'range loop
str(ptr to ptr) := to_binary_string(val(i));
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_binary_string;
end altera_europa_support_lib;
Common/sim/altera/libsrc/altera/altera_internal_syn.vhd
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-----------------------------------------------------------------------------
-- --
-- Copyright (c) 2003 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Declares utility package for internal Altera synthesis --
-- support. --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
PACKAGE altera_internal_syn is
-- Specfies a built-in pragma function that should replace a user-defined
-- subprogram during synthesis.
ATTRIBUTE synthesis_return : STRING;
-- If a subprogram specifies a synthesis_return attribute, it may also
-- use these additional attributes to fine-tune the behavior of a built-in
-- function.
-- Specifies the method for calculating the size of a unary or binary
-- built-in pragma function's result. The following values are supported:
--
-- LEFT: Use the size of the left operand
-- RIGHT: Use the size of the right operand
-- MAX_LEFT_RIGHT: Use the maximum of the left and right operands
ATTRIBUTE synthesis_result_size : STRING;
-- Flag that indicates if a type or an argument/result of a built-in pragma
-- function is signed (TRUE) or unsigned (FALSE).
ATTRIBUTE is_signed : BOOLEAN;
-- Flag that indicates if truncation should preserve the sign bit
attribute signed_truncation : BOOLEAN;
END altera_internal_syn;
Common/sim/altera/libsrc/altera/altera_primitives.vhd
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Common/sim/altera/libsrc/altera/altera_primitives_components.vhd
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
dont_touch : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
Common/sim/altera/libsrc/altera/altera_standard_functions.vhd
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
library std;
use std.standard.all;
package altera_standard_functions is
function maximum (L, R: integer) return integer;
function minimum (L, R: integer) return integer;
end altera_standard_functions;
package body altera_standard_functions is
function maximum (L, R: integer) return integer is
begin
if L > R then
return L;
else
return R;
end if;
end maximum;
function minimum (L, R: integer) return integer is
begin
if L > R then
return R;
else
return L;
end if;
end minimum;
end altera_standard_functions;
Common/sim/altera/libsrc/altera/altera_syn_attributes.vhd
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 2006 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Package containing Attribute Declarations for all --
-- attributes that control Quartus II Integrated Synthesis. --
-- Please refer to the Quartus II Help for documentation --
-- on using these attributes. --
-- --
-- --
-----------------------------------------------------------------------------
library std;
use std.standard.all;
PACKAGE altera_syn_attributes is
-- Directs Quartus II to implement input, output, and output
-- enable registers in I/O cells that have fast, direct connections to
-- an I/O pin, when possible
ATTRIBUTE useioff : BOOLEAN;
-- Prevents Quartus II from minimizing or removing a register
ATTRIBUTE preserve : BOOLEAN;
-- Prevents Quartus II from removing a dangling register
ATTRIBUTE noprune : BOOLEAN;
-- Prevents Quartus II from merging a register with a duplicate
ATTRIBUTE dont_merge : BOOLEAN;
-- Prevents Quartus II from replicating a register to improve timing
ATTRIBUTE dont_replicate : BOOLEAN;
-- Prevents Quartus II from retiming a register
ATTRIBUTE dont_retime : BOOLEAN;
-- Identifies the critical clock enable signal for a register. The
-- Quartus II software will attempt to connect this signal to the
-- dedicated clock enable port.
ATTRIBUTE direct_enable : BOOLEAN;
-- Prevents Quartus II from minimizing or removing a particular
-- signal net during combinational logic optimization
ATTRIBUTE keep : BOOLEAN;
-- Sets a fan-out limit on a register or net.
ATTRIBUTE maxfan : NATURAL;
-- Controls the implementation of a multiplication (*) operations in VHDL
ATTRIBUTE multstyle : STRING;
-- Controls the implementation of inferred memories
ATTRIBUTE ramstyle : STRING;
-- Controls the implementation of inferred ROMs
ATTRIBUTE romstyle : STRING;
-- Specifies a Memory Initialization File (.mif) for an inferred RAM
ATTRIBUTE ram_init_file : STRING;
-- Assigns a logic encoding to an enumerated type. Prevents state
-- machine extraction for all objects with the enumerated type.
ATTRIBUTE enum_encoding : STRING;
-- Assigns a state encoding to an enumerated type that models the states
-- of an extracted state machine.
ATTRIBUTE syn_encoding : STRING;
-- Specifies device pin assignments for a VHDL entity port
ATTRIBUTE chip_pin : STRING;
-- Applies an arbitrary number of Quartus Settings File (QSF) assignments
-- to a signal, entity, architecture, instance, or inferred register
ATTRIBUTE altera_attribute : STRING;
END altera_syn_attributes;
Common/sim/altera/libsrc/altera/maxplus2.vhd
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Common/sim/altera/libsrc/altera/megacore.vhd
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-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1996 by Altera Corp. All rights reserved. --
-- --
-- --
-- Description: Package file for Altera mega functions. --
-- --
-- --
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package megacore is
component a16450
port (
mr : IN std_logic;
clk : IN std_logic;
a : IN std_logic_vector(2 downto 0);
din : IN std_logic_vector(7 downto 0);
cs0 : IN std_logic;
cs1 : IN std_logic;
ncs2 : IN std_logic;
nads : IN std_logic;
rd : IN std_logic;
nrd : IN std_logic;
wr : IN std_logic;
nwr : IN std_logic;
sin : IN std_logic;
rclk : IN std_logic;
ncts : IN std_logic;
ndsr : IN std_logic;
ndcd : IN std_logic;
nri : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
ddis : OUT std_logic;
csout : OUT std_logic;
sout : OUT std_logic;
nbaudout : OUT std_logic;
nrts : OUT std_logic;
ndtr : OUT std_logic;
nout1 : OUT std_logic;
nout2 : OUT std_logic;
intr : OUT std_logic
);
end component;
component a6402
port (
cls1 : IN std_logic;
cls2 : IN std_logic;
crl : IN std_logic;
ndrr : IN std_logic;
epe : IN std_logic;
mr : IN std_logic;
pi : IN std_logic;
rrc : IN std_logic;
rri : IN std_logic;
sbs : IN std_logic;
tbr : IN std_logic_vector(7 downto 0);
ntbrl : IN std_logic;
trc : IN std_logic;
dr : OUT std_logic;
fe : OUT std_logic;
oe : OUT std_logic;
pe : OUT std_logic;
rbr : OUT std_logic_vector(7 downto 0);
tbre : OUT std_logic;
tro : OUT std_logic;
tre : OUT std_logic
);
end component;
component a6850
port (
nreset : IN std_logic;
di : IN std_logic_vector(7 downto 0);
e : IN std_logic;
rnw : IN std_logic;
cs : IN std_logic_vector(2 downto 0);
rs : IN std_logic;
txclk : IN std_logic;
rxclk : IN std_logic;
rxdata : IN std_logic;
ncts : IN std_logic;
ndcd : IN std_logic;
do : OUT std_logic_vector(7 downto 0);
nirq : OUT std_logic;
txdata : OUT std_logic;
nrts : OUT std_logic
);
end component;
component a8237
port (
reset : IN std_logic;
clk : IN std_logic;
ncs : IN std_logic;
niorin : IN std_logic;
niowin : IN std_logic;
ready : IN std_logic;
hlda : IN std_logic;
neopin : IN std_logic;
ain : IN std_logic_vector(3 downto 0);
dreq : IN std_logic_vector(3 downto 0);
dbin : IN std_logic_vector(7 downto 0);
dbout : OUT std_logic_vector(7 downto 0);
dben : OUT std_logic;
aout : OUT std_logic_vector(7 downto 0);
hrq : OUT std_logic;
dack : OUT std_logic_vector(3 downto 0);
aen : OUT std_logic;
adstb : OUT std_logic;
niorout : OUT std_logic;
niowout : OUT std_logic;
nmemr : OUT std_logic;
nmemw : OUT std_logic;
neopout : OUT std_logic;
dmaenable : OUT std_logic
);
end component;
component a8251
port (
clk : IN std_logic;
nreset : IN std_logic;
nwr : IN std_logic;
nrd : IN std_logic;
ncs : IN std_logic;
cnd : IN std_logic;
ndsr : IN std_logic;
ncts : IN std_logic;
extsyncd : IN std_logic;
ntxc : IN std_logic;
nrxc : IN std_logic;
rxd : IN std_logic;
din : IN std_logic_vector(7 downto 0);
txd : OUT std_logic;
txrdy : OUT std_logic;
txempty : OUT std_logic;
rxrdy : OUT std_logic;
ndtr : OUT std_logic;
nrts : OUT std_logic;
syn_brk : OUT std_logic;
nen : OUT std_logic;
dout : OUT std_logic_vector(7 downto 0)
);
end component;
component a8255
port (
reset : IN std_logic;
clk : IN std_logic;
ncs : IN std_logic;
nrd : IN std_logic;
nwr : IN std_logic;
a : IN std_logic_vector(1 downto 0);
din : IN std_logic_vector(7 downto 0);
pain : IN std_logic_vector(7 downto 0);
pbin : IN std_logic_vector(7 downto 0);
pcin : IN std_logic_vector(7 downto 0);
dout : OUT std_logic_vector(7 downto 0);
paout : OUT std_logic_vector(7 downto 0);
paen : OUT std_logic;
pbout : OUT std_logic_vector(7 downto 0);
pben : OUT std_logic;
pcout : OUT std_logic_vector(7 downto 0);
pcen : OUT std_logic_vector(7 downto 0)
);
end component;
component rgb2ycrcb
port (
R : IN std_logic_vector(7 downto 0);
G : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic := '0';
ACLR : IN std_logic := '0';
Y : OUT std_logic_vector(15 downto 0);
Cr: OUT std_logic_vector(14 downto 0);
Cb: OUT std_logic_vector(14 downto 0)
);
end component;
component ycrcb2rgb
port (
Y : IN std_logic_vector(7 downto 0);
CR : IN std_logic_vector(7 downto 0);
CB : IN std_logic_vector(7 downto 0);
CLOCK : IN std_logic := '0';
ACLR : IN std_logic := '0';
R : OUT std_logic_vector(16 downto 0);
G: OUT std_logic_vector(16 downto 0);
B: OUT std_logic_vector(16 downto 0)
);
end component;
component a8259
port (
nmrst, clk, ncs, nwr, nrd, a0, nsp, ninta : IN std_logic;
casin : IN std_logic_vector(2 downto 0);
din, ir : IN std_logic_vector(7 downto 0);
nen, cas_en, int : OUT std_logic;
dout : OUT std_logic_vector(7 downto 0);
casout : OUT std_logic_vector(7 downto 0)
);
end component;
component fft
generic (
WIDTH_DATA : POSITIVE;
WIDTH_TWIDDLE : POSITIVE;
PIPE_DATA : INTEGER;
PIPE_TWIDDLE : INTEGER;
WIDTH_EXPONENT : POSITIVE;
WIDTH_ADD : POSITIVE;
EXPONENT_INITIAL_VALUE : INTEGER
);
port (
clock : IN std_logic := '0';
start_fft : IN std_logic;
data_left_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_left_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_right_in_re : IN std_logic_vector(WIDTH_DATA-1 downto 0);
data_right_in_im : IN std_logic_vector(WIDTH_DATA-1 downto 0);
twiddle_re : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
twiddle_im : IN std_logic_vector(WIDTH_TWIDDLE-1 downto 0);
done : OUT std_logic;
data_direction : OUT std_logic;
we_left : OUT std_logic;
add_left : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
we_right : OUT std_logic;
add_right : OUT std_logic_vector(WIDTH_ADD-1 downto 0);
add_twiddle : OUT std_logic_vector(WIDTH_ADD-2 downto 0);
data_out_re : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
data_out_im : OUT std_logic_vector(WIDTH_DATA-1 downto 0);
exponent : OUT std_logic_vector(WIDTH_EXPONENT-1 downto 0)
);
end component;
end megacore;