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git-svn-id: http://moon:8086/svn/vhdl/trunk@1417 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 11:01:11 +00:00
parent d61b3c2e0c
commit 097032e4d5
7 changed files with 305 additions and 0 deletions
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projects/xst_bug/src/xst_bad_01.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:32 07/10/2006
-- Design Name:
-- Module Name: fix_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package my_pkg is
type my_t is array (integer range <>) of std_logic;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_pkg.all;
entity top is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in my_t (0 downto -15);
dout : out my_t (0 downto -15));
end top;
architecture Behavioral of top is
begin
process(clk, rst, din)
variable var1 : my_t (0 downto -15) := (others => '0');
begin
if (rst = '1') then
var1 := (others => '0');
-- dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
elsif rising_edge(clk) then
dout <= var1;
var1 := din;
end if;
end process;
end Behavioral;
projects/xst_bug/src/xst_bad_02.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:32 07/10/2006
-- Design Name:
-- Module Name: fix_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package my_pkg is
type my_t is array (integer range <>) of std_logic;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_pkg.all;
entity top is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in my_t (0 downto -15);
dout : out my_t (0 downto -15));
end top;
architecture Behavioral of top is
signal sig1, sig2 : my_t (0 downto -15) := (others => '0');
begin
process(clk, rst, din)
begin
if (rst = '1') then
sig1 <= (others => '0');
sig2 <= (others => '0');
-- dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
elsif rising_edge(clk) then
dout <= sig1;
sig1 <= din;
end if;
end process;
end Behavioral;
projects/xst_bug/src/xst_good_01.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:32 07/10/2006
-- Design Name:
-- Module Name: fix_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package my_pkg is
type my_t is array (integer range <>) of std_logic;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_pkg.all;
entity top is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in my_t (0 downto -15);
dout : out my_t (0 downto -15));
end top;
architecture Behavioral of top is
signal sig1 : my_t (0 downto -15) := (others => '0');
begin
process(clk, rst, din)
begin
if (rst = '1') then
sig1 <= (others => '0');
-- dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
elsif rising_edge(clk) then
dout <= sig1;
sig1 <= din;
end if;
end process;
end Behavioral;
projects/xst_bug/src/xst_good_02.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:01:32 07/10/2006
-- Design Name:
-- Module Name: fix_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package my_pkg is
type my_t is array (integer range <>) of std_logic;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_pkg.all;
entity top is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
din : in my_t (0 downto -15);
dout : out my_t (0 downto -15));
end top;
architecture Behavioral of top is
signal sig1, sig2 : my_t (0 downto -15) := (others => '0');
begin
process(clk, rst, din)
begin
if (rst = '1') then
sig1 <= (others => '0');
sig2 <= (others => '0');
-- dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
elsif rising_edge(clk) then
dout <= sig1;
sig1 <= din;
end if;
end process;
end Behavioral;