- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1417 cc03376c-175c-47c8-b038-4cd826a8556b

projects/xst_bug/project/top.lso

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+work

projects/xst_bug/project/top.prj

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+vhdl work "xst_bad_02.vhd"

projects/xst_bug/project/top.xst

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+set -tmpdir ./xst/projnav.tmp
+set -xsthdpdir ./xst
+run
+-ifn top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso top.lso
+-keep_hierarchy NO
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-mux_extract YES
+-resource_sharing YES
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5

projects/xst_bug/src/xst_bad_01.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    14:01:32 07/10/2006 
+-- Design Name: 
+-- Module Name:    fix_top - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package my_pkg is
+	type my_t is array (integer range <>) of std_logic;
+end package;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.my_pkg.all;
+
+entity top is
+    Port ( rst : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           din : in  my_t (0 downto -15);
+           dout : out  my_t (0 downto -15));
+
+end top;
+
+architecture Behavioral of top is
+
+begin
+
+process(clk, rst, din)
+variable var1 : my_t (0 downto -15) := (others => '0');
+
+begin
+	if (rst = '1') then
+		var1 := (others => '0');
+--		dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
+	elsif rising_edge(clk) then
+		dout <= var1;
+		var1 := din;
+	end if;
+	
+end process;
+
+end Behavioral;
+

projects/xst_bug/src/xst_bad_02.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    14:01:32 07/10/2006 
+-- Design Name: 
+-- Module Name:    fix_top - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package my_pkg is
+	type my_t is array (integer range <>) of std_logic;
+end package;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.my_pkg.all;
+
+entity top is
+    Port ( rst : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           din : in  my_t (0 downto -15);
+           dout : out  my_t (0 downto -15));
+
+end top;
+
+architecture Behavioral of top is
+signal sig1, sig2 : my_t (0 downto -15) := (others => '0');
+
+begin
+
+process(clk, rst, din)
+
+begin
+	if (rst = '1') then
+		sig1 <= (others => '0');
+		sig2 <= (others => '0');
+--		dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
+	elsif rising_edge(clk) then
+		dout <= sig1;
+		sig1 <= din;
+	end if;
+	
+end process;
+
+end Behavioral;
+

projects/xst_bug/src/xst_good_01.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    14:01:32 07/10/2006 
+-- Design Name: 
+-- Module Name:    fix_top - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package my_pkg is
+	type my_t is array (integer range <>) of std_logic;
+end package;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.my_pkg.all;
+
+entity top is
+    Port ( rst : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           din : in  my_t (0 downto -15);
+           dout : out  my_t (0 downto -15));
+
+end top;
+
+architecture Behavioral of top is
+
+signal sig1 : my_t (0 downto -15) := (others => '0');
+
+begin
+
+process(clk, rst, din)
+
+begin
+	if (rst = '1') then
+		sig1 <= (others => '0');
+--		dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
+	elsif rising_edge(clk) then
+		dout <= sig1;
+		sig1 <= din;
+	end if;
+	
+end process;
+
+end Behavioral;
+

projects/xst_bug/src/xst_good_02.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    14:01:32 07/10/2006 
+-- Design Name: 
+-- Module Name:    fix_top - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package my_pkg is
+	type my_t is array (integer range <>) of std_logic;
+end package;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.my_pkg.all;
+
+entity top is
+    Port ( rst : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           din : in  my_t (0 downto -15);
+           dout : out  my_t (0 downto -15));
+
+end top;
+
+architecture Behavioral of top is
+
+signal sig1, sig2 : my_t (0 downto -15) := (others => '0');
+
+begin
+
+process(clk, rst, din)
+
+begin
+	if (rst = '1') then
+		sig1 <= (others => '0');
+		sig2 <= (others => '0');
+--		dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
+	elsif rising_edge(clk) then
+		dout <= sig1;
+		sig1 <= din;
+	end if;
+	
+end process;
+
+end Behavioral;
+