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- added clkgen for vga

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git-svn-id: http://moon:8086/svn/vhdl/trunk@587 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 22:10:12 +00:00
parent c418244065
commit 06fccfd7af
1 changed files with 115 additions and 83 deletions
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projects/mips_sys/src/mips_sys_sim.vhd
+115 -83
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@@ -45,7 +45,9 @@ GENERIC
( (
sys_freq : integer := 100E6; sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0; ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6 ddr_frequency_hz : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_72
); );
PORT PORT
( (
@@ -305,7 +307,6 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT vga_frontend64 COMPONENT vga_frontend64
GENERIC GENERIC
( (
sys_freq : integer;
fifo_depth : integer; fifo_depth : integer;
fifo_almost_full_thresh : natural; fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural; fifo_almost_empty_thresh : natural;
@@ -342,7 +343,8 @@ ARCHITECTURE behavior OF mips_sys IS
SDAT_O : out unsigned(31 downto 0); SDAT_O : out unsigned(31 downto 0);
-- VGA signals -- VGA signals
vga_clk_out : out std_logic; vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0); vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0);
@@ -354,11 +356,14 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT; END COMPONENT;
signal nmi : std_logic; signal nmi : std_logic;
signal rst : std_logic;
signal clk : std_logic;
signal eb : std_logic; signal eb : std_logic;
signal clk270 : std_logic; signal sdram_clk_lock : std_logic;
signal clk270var : std_logic; signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_clk_prebuf : std_logic;
signal vga_clk_lock : std_logic;
signal rst_in : std_logic; signal rst_in : std_logic;
signal int_timer : std_logic; signal int_timer : std_logic;
signal int_uart0 : std_logic; signal int_uart0 : std_logic;
@@ -391,6 +396,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
-- J-Bus signals -- J-Bus signals
signal CLK_O : std_logic;
signal RST_O : std_logic;
signal INT : unsigned(5 downto 0); signal INT : unsigned(5 downto 0);
signal MDAT_I : word_t; signal MDAT_I : word_t;
signal MDAT_O : word_t; signal MDAT_O : word_t;
@@ -512,7 +519,6 @@ BEGIN
sys_error <= debug; sys_error <= debug;
nmi <= not sys_rst_n_in; nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
rst <= not locked;
sys_usb_rstn <= not gpo1(0); sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1'; sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2); ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
@@ -522,11 +528,13 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O; SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
CLK_O <= sys_clk_in;
RST_O <= not (sdram_clk_lock and vga_clk_lock);
sys_flash_ssram_out: sys_flash_ssram_out:
process(clk) process(CLK_O)
begin begin
if rising_edge(clk) then if rising_edge(CLK_O) then
sys_flash_ssram_d <= (others => 'Z') after topad; sys_flash_ssram_d <= (others => 'Z') after topad;
sys_flash_ssram_oe_n <= '1'; sys_flash_ssram_oe_n <= '1';
sys_flash_ssram_we_n <= '1'; sys_flash_ssram_we_n <= '1';
@@ -568,10 +576,10 @@ sys_flash_ssram_out:
MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I;
arbiter_proc: arbiter_proc:
process(clk) process(CLK_O)
begin begin
if rising_edge(clk) then if rising_edge(CLK_O) then
if rst = '1' then if RST_O = '1' then
arb_gnt <= (others => '0'); arb_gnt <= (others => '0');
arb_idx <= 0; arb_idx <= 0;
elsif arb_req(arb_idx) = '0' then elsif arb_req(arb_idx) = '0' then
@@ -588,9 +596,9 @@ arbiter_proc:
end process; end process;
int_sample: int_sample:
process(clk) process(CLK_O)
begin begin
if rising_edge(clk) then if rising_edge(CLK_O) then
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4); INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
end if; end if;
end process; end process;
@@ -715,8 +723,8 @@ inst_mips_top: mips_top
debug => debug, debug => debug,
eb => eb, eb => eb,
nmi => nmi, nmi => nmi,
RST_I => rst, RST_I => RST_O,
CLK_I => clk, CLK_I => CLK_O,
ACK_I => ACK_I_cpu, ACK_I => ACK_I_cpu,
SRDY_I => SRDY_I_cpu, SRDY_I => SRDY_I_cpu,
MRDY_O => MRDY_O_cpu, MRDY_O => MRDY_O_cpu,
@@ -733,8 +741,8 @@ inst_mips_top: mips_top
inst_rom_wb : rom_wb inst_rom_wb : rom_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_rom, CYC_I => CYC_I_rom,
STB_I => STB_O, STB_I => STB_O,
ACK_O => ACK_O_rom, ACK_O => ACK_O_rom,
@@ -748,8 +756,8 @@ inst_rom_wb : rom_wb
inst_lcd_port: lcd_port inst_lcd_port: lcd_port
PORT MAP PORT MAP
( (
clk => clk, clk => CLK_O,
rst => rst, rst => RST_O,
we => '0', we => '0',
din => X"00", din => X"00",
dout => open, dout => open,
@@ -762,8 +770,8 @@ inst_lcd_port: lcd_port
inst_gpio_wb : gpio_wb inst_gpio_wb : gpio_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_gpio, CYC_I => CYC_I_gpio,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
@@ -791,8 +799,8 @@ inst_flash_port : flash_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_flash, CYC_I => CYC_I_flash,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
@@ -824,8 +832,8 @@ inst_usb_port : async_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_usb, CYC_I => CYC_I_usb,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
@@ -849,8 +857,8 @@ inst_usb_port : async_port_wb
inst_uart_wb_0 : uart_wb inst_uart_wb_0 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_uart0, CYC_I => CYC_I_uart0,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
@@ -869,8 +877,8 @@ inst_uart_wb_0 : uart_wb
inst_uart_wb_1 : uart_wb inst_uart_wb_1 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_uart1, CYC_I => CYC_I_uart1,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
@@ -889,8 +897,8 @@ inst_uart_wb_1 : uart_wb
inst_uart_wb_2 : uart_wb inst_uart_wb_2 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_uart2, CYC_I => CYC_I_uart2,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
@@ -915,8 +923,8 @@ inst_ssram_port_wb : entity work.ssram_port_wb
PORT MAP PORT MAP
( (
-- J-Bus domain -- J-Bus domain
RST_I => rst, RST_I => RST_O,
CLK_I => clk, CLK_I => CLK_O,
CYC_I => CYC_I_ssram, CYC_I => CYC_I_ssram,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
@@ -948,6 +956,27 @@ inst_ssram_port_wb : entity work.ssram_port_wb
ssram_bw_n => sys_ssram_bw_n ssram_bw_n => sys_ssram_bw_n
); );
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
clk_in => CLK_O, -- system clock (e.g. 100MHz), from board
clk_fb_in => sys_sdr_clk_fb, -- feedback clock
clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => sdram_clk_lock, -- DCM locked status
error_out => open
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP GENERIC MAP
( (
@@ -957,72 +986,74 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
) )
PORT MAP PORT MAP
( (
RST_I => rst, RST_I => RST_O,
CLK_I => clk, CLK_I => CLK_O,
CLK270_I => clk270,
CLK270VAR_I => clk270var, SDRAM_CLK0_I => sdram_clk0,
SDRAM_CLK270_I => sdram_clk270,
SDRAM_CLK270VAR_I => sdram_clk270var,
CYC_I => CYC_I_sdram, CYC_I => CYC_I_sdram,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_I_sdram, SEL_I => SEL_I_sdram,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_sdram, ACK_O => ACK_O_sdram,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SRDY_O => SRDY_O_sdram, SRDY_O => SRDY_O_sdram,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => SDAT_I_sdram, DAT_I => SDAT_I_sdram,
DAT_O => SDAT_O_sdram, DAT_O => SDAT_O_sdram,
-- SDRAM signals -- SDRAM signals
sd_clk_p => sys_sdr_clk_p, sd_clk_p => sys_sdr_clk_p,
sd_clk_n => sys_sdr_clk_n, sd_clk_n => sys_sdr_clk_n,
sd_cke => sys_sdr_cke_q, sd_cke => sys_sdr_cke_q,
sd_cs_n => sys_sdr_cs_qn, sd_cs_n => sys_sdr_cs_qn,
sd_cas_n => sys_sdr_cas_qn, sd_cas_n => sys_sdr_cas_qn,
sd_ras_n => sys_sdr_ras_qn, sd_ras_n => sys_sdr_ras_qn,
sd_we_n => sys_sdr_we_qn, sd_we_n => sys_sdr_we_qn,
sd_addr => sys_sdr_a_q, sd_addr => sys_sdr_a_q,
sd_ba => sys_sdr_ba_q, sd_ba => sys_sdr_ba_q,
sd_dm => sys_sdr_dm_q, sd_dm => sys_sdr_dm_q,
sd_dqs => sys_sdr_dqs_q, sd_dqs => sys_sdr_dqs_q,
sd_data => sys_sdr_data sd_data => sys_sdr_data
); );
inst_clockgen : entity work.clockgen inst_clkgen: entity work.clkgen
GENERIC MAP GENERIC MAP
( (
sys1_phaseshift => 0, clk_in_freq_hz => sys_freq,
frequency_hz => 100E6 clk_out_freq_hz => tsvga.f_pxl_clk
) )
PORT MAP PORT MAP
( (
-- Clocks and Reset rst => rst_in,
rst => rst_in, -- external async reset, low active clk_in => CLK_O,
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board clk_out => vga_clk_prebuf,
clk_fb_in => sys_sdr_clk_fb, -- feedback clock locked => vga_clk_lock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° );
sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° BUFG_out_clk : BUFG
sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° port map
locked_out => locked, -- DCM locked status (
error_out => open O => vga_clk, -- Clock buffer output
I => vga_clk_prebuf -- Clock buffer input
); );
inst_vga_frontend : vga_frontend64 inst_vga_frontend : vga_frontend64
GENERIC MAP GENERIC MAP
( (
sys_freq => 100E6,
fifo_depth => 2048, fifo_depth => 2048,
fifo_almost_full_thresh => 1860, fifo_almost_full_thresh => 1860,
fifo_almost_empty_thresh => 256, fifo_almost_empty_thresh => 256,
tsvga => ts_vga_testbench tsvga => tsvga
) )
PORT MAP PORT MAP
( (
-- System signals -- System signals
RST_I => rst, RST_I => RST_O,
CLK_I => clk, CLK_I => CLK_O,
-- JBUS Master signals -- JBUS Master signals
CYC_O => CYC_O_vga, CYC_O => CYC_O_vga,
@@ -1049,7 +1080,8 @@ inst_vga_frontend : vga_frontend64
SDAT_O => SDAT_O_vga, SDAT_O => SDAT_O_vga,
-- VGA signals -- VGA signals
vga_clk_out => sys_vga_clk, vga_clk_in => vga_clk,
vga_clk_ce => vga_clk_lock,
vga_red => sys_vga_red, vga_red => sys_vga_red,
vga_green => sys_vga_green, vga_green => sys_vga_green,
vga_blue => sys_vga_blue, vga_blue => sys_vga_blue,
@@ -1067,8 +1099,8 @@ inst_ac97_wb : entity work.ac97_wb
PORT MAP PORT MAP
( (
-- J-Bus domain -- J-Bus domain
CLK_I => clk, CLK_I => CLK_O,
RST_I => rst, RST_I => RST_O,
CYC_I => CYC_I_ac97, CYC_I => CYC_I_ac97,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,