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- fixed timing in config

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- fixed data drive

git-svn-id: http://moon:8086/svn/vhdl/trunk@1212 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 13:13:17 +00:00
parent bd65d611dd
commit 06bc5d193e
2 changed files with 2 additions and 18 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
+1 -17
View File
@@ -65,7 +65,6 @@ architecture tech of sdram_phy is
signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0); signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal part_ctrl_reg : part_ctrl_t; signal part_ctrl_reg : part_ctrl_t;
signal we_reg : std_logic; signal we_reg : std_logic;
signal read_en : std_logic;
signal clk0 : std_logic; signal clk0 : std_logic;
signal clk0_s : std_logic; signal clk0_s : std_logic;
@@ -151,20 +150,7 @@ DATA_DRIVE_GEN:
process(clk0) process(clk0)
begin begin
if falling_edge(clk0) then if falling_edge(clk0) then
drive <= we_reg; drive <= phy_ctrl.drive_en;
end if;
end process;
DQS_DRIVE_GEN:
process(clk0)
variable p : unsigned(1 downto 0);
begin
if rising_edge(clk0) then
if phy_ctrl.drive_en = '1' then
p := (others => '1');
else
p := p(p'left-1 downto 0) & '0';
end if;
end if; end if;
end process; end process;
@@ -239,7 +225,6 @@ misc_flags_and_data_out:
if rising_edge(clk0) then if rising_edge(clk0) then
if rst0 = '1' then if rst0 = '1' then
p := (others => '0'); p := (others => '0');
read_en <= '0';
phy_out.rd_data_we <= '0'; phy_out.rd_data_we <= '0';
phy_out.wr_data_re <= '0'; phy_out.wr_data_re <= '0';
else else
@@ -252,7 +237,6 @@ misc_flags_and_data_out:
end if; end if;
phy_out.wr_data_re <= phy_ctrl.we; phy_out.wr_data_re <= phy_ctrl.we;
phy_out.rd_data_we <= p(3); phy_out.rd_data_we <= p(3);
read_en <= p(1);
if phy_ctrl.re = '1' then if phy_ctrl.re = '1' then
p := p(p'left-1 downto 0) & '1'; p := p(p'left-1 downto 0) & '1';
else else
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+1 -1
View File
@@ -64,7 +64,7 @@ package sdram_config is
-- These values are for your SDRAM part (see datasheet) -- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks] constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns] constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns] constant TRAS : real := 50.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns] constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks] constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0; -- active to read or write delay [ns] constant TRCD : real := 20.0; -- active to read or write delay [ns]