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- made time specs in SDRAM_config independent of SDRAM clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@717 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 12:41:09 +00:00
parent 13c772be6e
commit 010edebc97
9 changed files with 67 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+24 -2
View File
@@ -29,8 +29,13 @@ use work.sdram_config.all;
use work.sdram_types.all; use work.sdram_types.all;
entity sdram_cmd is entity sdram_cmd is
Generic (BL : natural := 2); Generic
Port ( (
f_sdrclk_hz : natural := 100E6;
BL : natural := 2
);
Port
(
rst : in STD_LOGIC; rst : in STD_LOGIC;
clk : in STD_LOGIC; clk : in STD_LOGIC;
enable : in STD_LOGIC; enable : in STD_LOGIC;
@@ -60,6 +65,23 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic; signal burst_load_en : std_logic;
signal burst_finished : std_logic; signal burst_finished : std_logic;
subtype cycle_cnt_t is natural range 0 to 10;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => (0 ),
SD_NOP => (0 ),
SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk_hz)-1),
SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk_hz)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk_hz)-1),
SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk_hz)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk_hz)-1)
);
begin begin
u_tag_out <= u_tag_in; u_tag_out <= u_tag_in;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+9 -9
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------ -- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125; -- us constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s]
-- These values are for your SDRAM part (see datasheet) -- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks] constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period constant TRP : real := 20.0E-9; -- precharge command period [s]
constant TRAS : positive := 4; -- active to precharge delay constant TRAS : real := 45.0E-9; -- active to precharge delay [s]
constant TRFC : positive := 8; -- auto refresh command period constant TRFC : real := 75.0E-9; -- auto refresh command period [s]
constant TMRD : positive := 2; -- load mode register command cylce time constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : positive := 2; -- active to read or write delay ! constant TRCD : real := 20.0E-9; -- active to read or write delay [s]
constant TWR : positive := 2; -- write recovery time constant TWR : real := 15.0E-9; -- write recovery time [s]
constant PWR_UP_WAIT : natural := 1; -- µs constant PWR_UP_WAIT : real := 1.0E-6; -- [s]
subtype user_tag_t is unsigned(3 downto 0); subtype user_tag_t is unsigned(3 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+3 -3
View File
@@ -32,7 +32,7 @@ use work.utils_pkg.all;
entity sdram_ctrl is entity sdram_ctrl is
Generic Generic
( (
f_sysclk : natural := 100E6; f_sysclk_hz : natural := 100E6;
BL : natural := 2 BL : natural := 2
); );
Port ( Port (
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t; signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk_hz);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic; signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic; signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic; signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic; signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk_hz);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic; signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic; signal refresh_cnt_rst : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+4 -2
View File
@@ -33,7 +33,8 @@ entity sdram_ctrl_frontend64_wb is
Generic Generic
( (
BL : natural := 2; BL : natural := 2;
f_sysclk : natural := 100E6; f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
fifo_depth : integer := 4 fifo_depth : integer := 4
); );
Port Port
@@ -204,7 +205,8 @@ begin
Generic map Generic map
( (
BL => BL, BL => BL,
f_sysclk => f_sysclk, f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
fifo_depth => fifo_depth fifo_depth => fifo_depth
) )
Port map Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+4 -2
View File
@@ -33,7 +33,8 @@ entity sdram_ctrl_frontend_wb is
Generic Generic
( (
BL : natural := 2; BL : natural := 2;
f_sysclk : natural := 100E6; f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
fifo_depth : integer := 4 fifo_depth : integer := 4
); );
Port Port
@@ -204,7 +205,8 @@ begin
Generic map Generic map
( (
BL => BL, BL => BL,
f_sysclk => f_sysclk, f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
fifo_depth => fifo_depth fifo_depth => fifo_depth
) )
Port map Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+5 -3
View File
@@ -32,7 +32,8 @@ entity sdram_ctrl_top is
Generic Generic
( (
BL : natural := 2; BL : natural := 2;
f_sysclk : natural := 100E6; f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
fifo_depth : natural := 3 fifo_depth : natural := 3
); );
Port Port
@@ -132,8 +133,8 @@ begin
inst_sdram_ctrl : entity work.sdram_ctrl inst_sdram_ctrl : entity work.sdram_ctrl
Generic map Generic map
( (
f_sysclk => 100E6, f_sysclk_hz => f_sysclk_hz,
BL => BL BL => BL
) )
Port map Port map
( (
@@ -179,6 +180,7 @@ begin
inst_sdram_cmd : entity work.sdram_cmd inst_sdram_cmd : entity work.sdram_cmd
Generic map Generic map
( (
f_sdrclk_hz => f_sdrclk_hz,
BL => BL BL => BL
) )
Port map Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+13 -17
View File
@@ -67,8 +67,6 @@ package sdram_types is
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype col_addr_t is unsigned(8 downto 0); subtype col_addr_t is unsigned(8 downto 0);
subtype cycle_cnt_t is natural range 0 to 10;
type phy_ctrl_t is type phy_ctrl_t is
record record
drive_en : std_logic; drive_en : std_logic;
@@ -108,21 +106,6 @@ package sdram_types is
SD_SR => ( '0', '0', '0', '1') SD_SR => ( '0', '0', '0', '1')
); );
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => ( 0 ),
SD_NOP => ( 0 ),
SD_LMR => ( TMRD-1 ),
SD_ACT => ( TRCD-1 ),
SD_READ => ( TCAS-1 ),
SD_WRITE => ( TWR-1 ),
SD_PRE => ( TRP-1 ),
SD_BST => ( 0 ),
SD_AR => ( TRFC-1 ),
SD_SR => ( TRFC-1 )
);
type init_seq_t is type init_seq_t is
record record
cmd : sdr_cmd_t; cmd : sdr_cmd_t;
@@ -130,4 +113,17 @@ package sdram_types is
wait_cycle : natural; wait_cycle : natural;
end record init_seq_t; end record init_seq_t;
function to_cycles(T_s : real; f_hz : natural) return natural;
end sdram_types;
package body sdram_types is
function to_cycles(T_s : real; f_hz : natural) return natural is
begin
return natural(0.5 + T_s*real(f_hz));
end to_cycles;
end sdram_types; end sdram_types;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+3 -2
View File
@@ -36,7 +36,7 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation -- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 8 ns; constant SDCLK_PERIOD : time := 7.5 ns;
constant BURST_LEN : natural := 2; constant BURST_LEN : natural := 2;
signal rst : std_logic := '1'; signal rst : std_logic := '1';
@@ -151,7 +151,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP GENERIC MAP
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => 100E6, f_sysclk_hz => 100E6,
f_sdrclk_hz => 133E6,
fifo_depth => 4 fifo_depth => 4
) )
PORT MAP PORT MAP
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+2 -1
View File
@@ -146,7 +146,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP GENERIC MAP
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => 100E6, f_sysclk_hz => 100E6,
f_sdrclk_hz => 100E6,
fifo_depth => 4 fifo_depth => 4
) )
PORT MAP PORT MAP