diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index d3d11ce..3cda76d 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -29,8 +29,13 @@ use work.sdram_config.all; use work.sdram_types.all; entity sdram_cmd is - Generic (BL : natural := 2); - Port ( + Generic + ( + f_sdrclk_hz : natural := 100E6; + BL : natural := 2 + ); + Port + ( rst : in STD_LOGIC; clk : in STD_LOGIC; enable : in STD_LOGIC; @@ -60,6 +65,23 @@ architecture behaviour of sdram_cmd is signal burst_load_en : std_logic; signal burst_finished : std_logic; + subtype cycle_cnt_t is natural range 0 to 10; + + type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; + constant TIMING : part_timing_array_t := + -- command cycle_cnt + ( SD_DESELECT => (0 ), + SD_NOP => (0 ), + SD_LMR => (TMRD-1 ), + SD_ACT => (to_cycles(TRCD, f_sdrclk_hz)-1), + SD_READ => (TCAS-1 ), + SD_WRITE => (to_cycles(TWR, f_sdrclk_hz)-1), + SD_PRE => (to_cycles(TRP, f_sdrclk_hz)-1), + SD_BST => (0 ), + SD_AR => (to_cycles(TRFC, f_sdrclk_hz)-1), + SD_SR => (to_cycles(TRFC, f_sdrclk_hz)-1) + ); + begin u_tag_out <= u_tag_in; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd index b0a6253..c8a0fc0 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd @@ -54,18 +54,18 @@ package sdram_config is -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us + constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s] -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time + constant TCAS : positive := 2; -- CAS latency [clocks] + constant TRP : real := 20.0E-9; -- precharge command period [s] + constant TRAS : real := 45.0E-9; -- active to precharge delay [s] + constant TRFC : real := 75.0E-9; -- auto refresh command period [s] + constant TMRD : positive := 2; -- load mode register command cylce time [clocks] + constant TRCD : real := 20.0E-9; -- active to read or write delay [s] + constant TWR : real := 15.0E-9; -- write recovery time [s] - constant PWR_UP_WAIT : natural := 1; -- µs + constant PWR_UP_WAIT : real := 1.0E-6; -- [s] subtype user_tag_t is unsigned(3 downto 0); diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd index 42ad1c9..bc9d8ba 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd @@ -32,7 +32,7 @@ use work.utils_pkg.all; entity sdram_ctrl is Generic ( - f_sysclk : natural := 100E6; + f_sysclk_hz : natural := 100E6; BL : natural := 2 ); Port ( @@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); signal st_ctrl, st_ctrl_next : ctrl_state_t; - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); + constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk_hz); signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; signal pwr_up_cnt_rst : std_logic; signal pwr_up_finished : std_logic; @@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is signal seq_rst_en : std_logic; signal seq_cnt_en : std_logic; - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); + constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk_hz); signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; signal refresh_request : std_logic; signal refresh_cnt_rst : std_logic; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index 936b508..da0ebcb 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -33,7 +33,8 @@ entity sdram_ctrl_frontend64_wb is Generic ( BL : natural := 2; - f_sysclk : natural := 100E6; + f_sysclk_hz : natural := 100E6; + f_sdrclk_hz : natural := 100E6; fifo_depth : integer := 4 ); Port @@ -204,7 +205,8 @@ begin Generic map ( BL => BL, - f_sysclk => f_sysclk, + f_sysclk_hz => f_sysclk_hz, + f_sdrclk_hz => f_sdrclk_hz, fifo_depth => fifo_depth ) Port map diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index 6d293d7..ae43e20 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -33,7 +33,8 @@ entity sdram_ctrl_frontend_wb is Generic ( BL : natural := 2; - f_sysclk : natural := 100E6; + f_sysclk_hz : natural := 100E6; + f_sdrclk_hz : natural := 100E6; fifo_depth : integer := 4 ); Port @@ -204,7 +205,8 @@ begin Generic map ( BL => BL, - f_sysclk => f_sysclk, + f_sysclk_hz => f_sysclk_hz, + f_sdrclk_hz => f_sdrclk_hz, fifo_depth => fifo_depth ) Port map diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index e0e1473..251af88 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -32,7 +32,8 @@ entity sdram_ctrl_top is Generic ( BL : natural := 2; - f_sysclk : natural := 100E6; + f_sysclk_hz : natural := 100E6; + f_sdrclk_hz : natural := 100E6; fifo_depth : natural := 3 ); Port @@ -132,8 +133,8 @@ begin inst_sdram_ctrl : entity work.sdram_ctrl Generic map ( - f_sysclk => 100E6, - BL => BL + f_sysclk_hz => f_sysclk_hz, + BL => BL ) Port map ( @@ -179,6 +180,7 @@ begin inst_sdram_cmd : entity work.sdram_cmd Generic map ( + f_sdrclk_hz => f_sdrclk_hz, BL => BL ) Port map diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd index d235d75..fcb28a4 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd @@ -67,8 +67,6 @@ package sdram_types is subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); subtype col_addr_t is unsigned(8 downto 0); - subtype cycle_cnt_t is natural range 0 to 10; - type phy_ctrl_t is record drive_en : std_logic; @@ -108,21 +106,6 @@ package sdram_types is SD_SR => ( '0', '0', '0', '1') ); - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - type init_seq_t is record cmd : sdr_cmd_t; @@ -130,4 +113,17 @@ package sdram_types is wait_cycle : natural; end record init_seq_t; + function to_cycles(T_s : real; f_hz : natural) return natural; + +end sdram_types; + +package body sdram_types is + + function to_cycles(T_s : real; f_hz : natural) return natural is + begin + + return natural(0.5 + T_s*real(f_hz)); + + end to_cycles; + end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd index 1de777d..4eeaec3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd @@ -36,7 +36,7 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is -- Number of user data words for simulation constant CLK_PERIOD : time := 10 ns; - constant SDCLK_PERIOD : time := 8 ns; + constant SDCLK_PERIOD : time := 7.5 ns; constant BURST_LEN : natural := 2; signal rst : std_logic := '1'; @@ -151,7 +151,8 @@ inst_clockgen : entity work.clockgen GENERIC MAP ( BL => BURST_LEN, - f_sysclk => 100E6, + f_sysclk_hz => 100E6, + f_sdrclk_hz => 133E6, fifo_depth => 4 ) PORT MAP diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd index 2a9d9bf..c5a8cc9 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd @@ -146,7 +146,8 @@ inst_clockgen : entity work.clockgen GENERIC MAP ( BL => BURST_LEN, - f_sysclk => 100E6, + f_sysclk_hz => 100E6, + f_sdrclk_hz => 100E6, fifo_depth => 4 ) PORT MAP