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- made time specs in SDRAM_config independent of SDRAM clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@717 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 12:41:09 +00:00
parent 13c772be6e
commit 010edebc97
9 changed files with 67 additions and 41 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+3 -3
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@@ -32,7 +32,7 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk : natural := 100E6;
f_sysclk_hz : natural := 100E6;
BL : natural := 2
);
Port (
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk_hz);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk_hz);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;