jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- made time specs in SDRAM_config independent of SDRAM clock

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@717 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 12:41:09 +00:00
parent 13c772be6e
commit 010edebc97
9 changed files with 67 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+24 -2
View File
@@ -29,8 +29,13 @@ use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_cmd is
Generic (BL : natural := 2);
Port (
Generic
(
f_sdrclk_hz : natural := 100E6;
BL : natural := 2
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
@@ -60,6 +65,23 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
subtype cycle_cnt_t is natural range 0 to 10;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => (0 ),
SD_NOP => (0 ),
SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk_hz)-1),
SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk_hz)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk_hz)-1),
SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk_hz)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk_hz)-1)
);
begin
u_tag_out <= u_tag_in;