- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1426 cc03376c-175c-47c8-b038-4cd826a8556b

projects/piso_sipo/src/tb_piso.vhd

@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:08:52 04/08/2007
+-- Design Name:   piso
+-- Module Name:   tb_piso.vhd
+-- Project Name:  piso_sipo
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: piso
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY tb_piso_vhd IS
+GENERIC ( width : integer := 8);
+END tb_piso_vhd;
+
+ARCHITECTURE behavior OF tb_piso_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT piso
+	GENERIC ( width : integer );
+	PORT(
+		rst		: in  STD_LOGIC;
+		clk		: in  STD_LOGIC;
+		pdi		: in  UNSIGNED (width-1 downto 0);
+		pvi		: in  STD_LOGIC;
+		prdyo	: out STD_LOGIC;
+		sdo		: out STD_LOGIC;
+		sso		: out STD_LOGIC;
+		srdyi	: in  STD_LOGIC
+		);
+	END COMPONENT;
+
+	CONSTANT CLK_PERIOD : time := 10 ns;
+	
+	--Inputs
+	SIGNAL rst :  std_logic := '1';
+	SIGNAL clk :  std_logic := '1';
+	SIGNAL pvi :  std_logic := '0';
+	SIGNAL srdyi :  std_logic := '0';
+	SIGNAL pdi :  UNSIGNED(width-1 downto 0) := (others=>'0');
+
+	--Outputs
+	SIGNAL prdyo :  std_logic;
+	SIGNAL sdo :  std_logic;
+	SIGNAL sso :  std_logic;
+	SIGNAL data : integer := 0;
+	
+BEGIN
+
+	clk_gen:
+	PROCESS
+	BEGIN
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	END PROCESS;
+		
+	-- Instantiate the Unit Under Test (UUT)
+	uut: piso 
+	GENERIC MAP( width => width )
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		pdi => pdi,
+		pvi => pvi,
+		prdyo => prdyo,
+		sdo => sdo,
+		sso => sso,
+		srdyi => srdyi
+	);
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 100 ns;
+		rst <= '0';
+		
+	
+		-- Place stimulus here
+
+		wait; -- will wait forever
+	END PROCESS;
+␍	
+	tb_srdy : process (rst, clk, sso)
+	variable count : integer := 0;
+	begin
+		if rst = '1' then
+			srdyi <= '0';
+			count := 20;
+		elsif rising_edge(clk) then
+			if srdyi = '1' then
+				if sso = '1' then
+					srdyi <= '0';
+				end if;
+			else
+				if count /= 0 then
+					count := count - 1;
+				else
+					srdyi <= '1';
+					count := 20;
+				end if;
+			end if;
+		end if;	
+	end process;
+		
+	tb_sig : process (rst, clk, prdyo)
+	begin
+		if rst = '1' then
+			data <= 0;
+		elsif rising_edge(clk) then
+			if prdyo = '1' then
+				data <= data + 1;
+			end if;
+		end if;	
+		pdi <= to_unsigned(data, pdi'length);
+		pvi <= prdyo;
+	end process;
+			
+END;