- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1426 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,133 @@
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----------------------------------------------------------------------------------
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-- Company:
|
||||
-- Engineer:
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||||
--
|
||||
-- Create Date: 15:26:08 04/08/2007
|
||||
-- Design Name:
|
||||
-- Module Name: piso - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
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||||
--
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||||
----------------------------------------------------------------------------------
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||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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||||
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---- Uncomment the following library declaration if instantiating
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||||
---- any Xilinx primitives in this code.
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||||
--library UNISIM;
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--use UNISIM.VComponents.all;
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entity piso is
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Generic ( width : integer := 8 );
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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pdi : in UNSIGNED (width-1 downto 0);
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||||
pvi : in STD_LOGIC;
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||||
prdyo : out STD_LOGIC;
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||||
sdo : out STD_LOGIC;
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sso : out STD_LOGIC;
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srdyi : in STD_LOGIC
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||||
);
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end piso;
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architecture Behavioral of piso is
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type sstate_t is (reset, idle, ready, sync, active);
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constant idle_pol : std_logic := '0';
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signal reg : UNSIGNED (width-1 downto 0);
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signal shift_en, counter_srst, counter_rdy : std_logic;
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signal sstate, sstate_next : sstate_t;
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||||
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begin
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par_in:
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process (rst, clk, pvi, reg, shift_en)
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begin
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if rst = '1' then
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reg <= (others => idle_pol);
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elsif rising_edge(clk) then
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if pvi = '1' then
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reg <= pdi;
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elsif shift_en = '1' then
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reg <= reg(width-2 downto 0) & idle_pol;
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end if;
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end if;
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sdo <= reg(width-1);
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end process;
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counter:
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process (rst, counter_srst, clk)
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variable counter : integer range 0 to width-1;
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begin
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if rst = '1' then
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counter_rdy <= '0';
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elsif rising_edge(clk) then
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if counter_srst = '1' then
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counter := width-4;
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counter_rdy <= '0';
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elsif counter /= 0 then
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counter := counter - 1;
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else
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counter_rdy <= '1';
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end if;
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end if;
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end process;
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ser_sm:
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process (rst, clk, pvi, sstate, counter_rdy, srdyi)
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begin
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sstate_next <= sstate;
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prdyo <= '0';
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sso <= '0';
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shift_en <= '0';
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counter_srst <= '1';
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case sstate is
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when reset =>
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sstate_next <= idle;
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when idle =>
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sstate_next <= ready;
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when ready =>
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prdyo <= srdyi;
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if pvi = '1' then
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sstate_next <= sync;
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end if;
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when sync =>
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sso <= '1';
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sstate_next <= active;
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shift_en <= '1';
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when active =>
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shift_en <= '1';
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counter_srst <= '0';
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if counter_rdy = '1' then
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sstate_next <= idle;
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end if;
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when others =>
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sstate_next <= idle;
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end case;
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||||
end process;
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||||
|
||||
state_proc:
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process (rst, clk, sstate_next)
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begin
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if rst = '1' then
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sstate <= reset;
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elsif rising_edge(clk) then
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sstate <= sstate_next;
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end if;
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end process;
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end Behavioral;
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||||
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@@ -0,0 +1,131 @@
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----------------------------------------------------------------------------------
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-- Company:
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||||
-- Engineer:
|
||||
--
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||||
-- Create Date: 19:55:49 04/08/2007
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||||
-- Design Name:
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||||
-- Module Name: sipo - Behavioral
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-- Project Name:
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||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
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||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
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||||
--
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||||
----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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||||
---- any Xilinx primitives in this code.
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||||
--library UNISIM;
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--use UNISIM.VComponents.all;
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entity sipo is
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Generic ( width : integer := 8 );
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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srdyo : out STD_LOGIC;
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sdi : in STD_LOGIC;
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ssi : in STD_LOGIC;
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prdyi : in STD_LOGIC;
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pvo : out STD_LOGIC;
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pdo : out UNSIGNED (width-1 downto 0)
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);
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end sipo;
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architecture Behavioral of sipo is
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type sstate_t is (reset, idle, ready, sync, active);
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constant idle_pol : std_logic := '0';
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signal reg : UNSIGNED (width-1 downto 0);
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signal pvalid, shift_en, counter_srst, counter_rdy : std_logic;
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signal sstate, sstate_next : sstate_t;
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begin
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par_out:
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process (rst, clk, sdi, reg, shift_en, pvalid)
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begin
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if rst = '1' then
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reg <= (others => idle_pol);
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pvo <= '0';
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elsif rising_edge(clk) then
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if shift_en = '1' then
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reg <= reg(width-2 downto 0) & sdi;
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end if;
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pvo <= pvalid;
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end if;
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pdo <= reg;
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end process;
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counter:
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process (rst, clk, counter_srst)
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variable counter : integer range 0 to width-1;
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begin
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if rst = '1' then
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counter_rdy <= '0';
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elsif rising_edge(clk) then
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if counter_srst = '1' then
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counter := width-4;
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counter_rdy <= '0';
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elsif counter /= 0 then
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counter := counter - 1;
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else
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counter_rdy <= '1';
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end if;
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||||
end if;
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||||
end process;
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ser_sm:
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process (rst, clk, ssi, sstate, counter_rdy, prdyi)
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begin
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sstate_next <= sstate;
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shift_en <= '1';
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pvalid <= '0';
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counter_srst <= ssi;
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srdyo <= '0';
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case sstate is
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||||
when reset =>
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sstate_next <= idle;
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when idle =>
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sstate_next <= ready;
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when ready =>
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srdyo <= prdyi;
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if ssi = '1' then
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sstate_next <= active;
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||||
end if;
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||||
when active =>
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if counter_rdy = '1' then
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sstate_next <= sync;
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end if;
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when sync =>
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pvalid <= '1';
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sstate_next <= idle;
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when others =>
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sstate_next <= idle;
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end case;
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end process;
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state_proc:
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process (rst, clk, sstate_next)
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begin
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if rst = '1' then
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sstate <= reset;
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elsif rising_edge(clk) then
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sstate <= sstate_next;
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end if;
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||||
end process;
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end Behavioral;
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@@ -0,0 +1,140 @@
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||||
--------------------------------------------------------------------------------
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||||
-- Company:
|
||||
-- Engineer:
|
||||
--
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||||
-- Create Date: 17:08:52 04/08/2007
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||||
-- Design Name: piso
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||||
-- Module Name: tb_piso.vhd
|
||||
-- Project Name: piso_sipo
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: piso
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
use IEEE.NUMERIC_STD.ALL;
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||||
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||||
ENTITY tb_piso_vhd IS
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||||
GENERIC ( width : integer := 8);
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||||
END tb_piso_vhd;
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||||
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||||
ARCHITECTURE behavior OF tb_piso_vhd IS
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||||
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||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT piso
|
||||
GENERIC ( width : integer );
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||||
PORT(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
pdi : in UNSIGNED (width-1 downto 0);
|
||||
pvi : in STD_LOGIC;
|
||||
prdyo : out STD_LOGIC;
|
||||
sdo : out STD_LOGIC;
|
||||
sso : out STD_LOGIC;
|
||||
srdyi : in STD_LOGIC
|
||||
);
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||||
END COMPONENT;
|
||||
|
||||
CONSTANT CLK_PERIOD : time := 10 ns;
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||||
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||||
--Inputs
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||||
SIGNAL rst : std_logic := '1';
|
||||
SIGNAL clk : std_logic := '1';
|
||||
SIGNAL pvi : std_logic := '0';
|
||||
SIGNAL srdyi : std_logic := '0';
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SIGNAL pdi : UNSIGNED(width-1 downto 0) := (others=>'0');
|
||||
|
||||
--Outputs
|
||||
SIGNAL prdyo : std_logic;
|
||||
SIGNAL sdo : std_logic;
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||||
SIGNAL sso : std_logic;
|
||||
SIGNAL data : integer := 0;
|
||||
|
||||
BEGIN
|
||||
|
||||
clk_gen:
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
END PROCESS;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
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||||
uut: piso
|
||||
GENERIC MAP( width => width )
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||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
pdi => pdi,
|
||||
pvi => pvi,
|
||||
prdyo => prdyo,
|
||||
sdo => sdo,
|
||||
sso => sso,
|
||||
srdyi => srdyi
|
||||
);
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
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||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 100 ns;
|
||||
rst <= '0';
|
||||
|
||||
|
||||
-- Place stimulus here
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
|
||||
|
||||
tb_srdy : process (rst, clk, sso)
|
||||
variable count : integer := 0;
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||||
begin
|
||||
if rst = '1' then
|
||||
srdyi <= '0';
|
||||
count := 20;
|
||||
elsif rising_edge(clk) then
|
||||
if srdyi = '1' then
|
||||
if sso = '1' then
|
||||
srdyi <= '0';
|
||||
end if;
|
||||
else
|
||||
if count /= 0 then
|
||||
count := count - 1;
|
||||
else
|
||||
srdyi <= '1';
|
||||
count := 20;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tb_sig : process (rst, clk, prdyo)
|
||||
begin
|
||||
if rst = '1' then
|
||||
data <= 0;
|
||||
elsif rising_edge(clk) then
|
||||
if prdyo = '1' then
|
||||
data <= data + 1;
|
||||
end if;
|
||||
end if;
|
||||
pdi <= to_unsigned(data, pdi'length);
|
||||
pvi <= prdyo;
|
||||
end process;
|
||||
|
||||
@@ -0,0 +1,187 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:08:52 04/08/2007
|
||||
-- Design Name: piso
|
||||
-- Module Name: tb_piso.vhd
|
||||
-- Project Name: piso_sipo
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: piso
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
ENTITY tb_sipo_vhd IS
|
||||
GENERIC ( width : integer := 8);
|
||||
END tb_sipo_vhd;
|
||||
|
||||
ARCHITECTURE behavior OF tb_sipo_vhd IS
|
||||
|
||||
-- Component Declaration for PISO
|
||||
COMPONENT piso
|
||||
GENERIC ( width : integer );
|
||||
PORT(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
pdi : in UNSIGNED (width-1 downto 0);
|
||||
pvi : in STD_LOGIC;
|
||||
prdyo : out STD_LOGIC;
|
||||
sdo : out STD_LOGIC;
|
||||
sso : out STD_LOGIC;
|
||||
srdyi : in STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT sipo
|
||||
GENERIC ( width : integer );
|
||||
PORT(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
srdyo : out STD_LOGIC;
|
||||
sdi : in STD_LOGIC;
|
||||
ssi : in STD_LOGIC;
|
||||
prdyi : in STD_LOGIC;
|
||||
pvo : out STD_LOGIC;
|
||||
pdo : out UNSIGNED (width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
CONSTANT CLK_PERIOD : time := 10 ns;
|
||||
|
||||
--Inputs
|
||||
SIGNAL rst : std_logic := '1';
|
||||
SIGNAL clk : std_logic := '1';
|
||||
SIGNAL sdi : std_logic := '0';
|
||||
SIGNAL ssi : std_logic := '0';
|
||||
SIGNAL pvi : std_logic := '0';
|
||||
SIGNAL srdyi : std_logic := '1';
|
||||
SIGNAL prdyi : std_logic := '1';
|
||||
SIGNAL pdi : UNSIGNED(width-1 downto 0) := (others=>'0');
|
||||
|
||||
--Outputs
|
||||
SIGNAL srdyo : std_logic;
|
||||
SIGNAL prdyo : std_logic;
|
||||
SIGNAL sdo : std_logic;
|
||||
SIGNAL sso : std_logic;
|
||||
SIGNAL pvo : std_logic;
|
||||
SIGNAL pdo : UNSIGNED(width-1 downto 0);
|
||||
SIGNAL data : integer := 0;
|
||||
SIGNAL data_out : UNSIGNED(width-1 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
clk_gen:
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
END PROCESS;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_piso: piso
|
||||
GENERIC MAP( width => width )
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
pdi => pdi,
|
||||
pvi => pvi,
|
||||
prdyo => prdyo,
|
||||
sdo => sdo,
|
||||
sso => sso,
|
||||
srdyi => srdyi
|
||||
);
|
||||
|
||||
uut: sipo
|
||||
GENERIC MAP( width => width )
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
srdyo => srdyo,
|
||||
sdi => sdi,
|
||||
ssi => ssi,
|
||||
pvo => pvo,
|
||||
pdo => pdo,
|
||||
prdyi => prdyi
|
||||
);
|
||||
|
||||
tb_prdy : process (rst, clk, pvo)
|
||||
variable count : integer := 0;
|
||||
begin
|
||||
if rst = '1' then
|
||||
prdyi <= '0';
|
||||
count := 10;
|
||||
elsif rising_edge(clk) then
|
||||
if pvo = '1' then
|
||||
prdyi <= pdi(0);
|
||||
end if;
|
||||
if count /= 0 then
|
||||
count := count - 1;
|
||||
else
|
||||
count := 53;
|
||||
prdyi <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sdi <= sdo;
|
||||
ssi <= sso;
|
||||
srdyi <= srdyo;
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 100 ns;
|
||||
rst <= '0';
|
||||
|
||||
|
||||
-- Place stimulus here
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
|
||||
tb_sig : process (rst, clk, prdyo)
|
||||
begin
|
||||
if rst = '1' then
|
||||
data <= 85;
|
||||
elsif rising_edge(clk) then
|
||||
if prdyo = '1' then
|
||||
data <= data + 1;
|
||||
end if;
|
||||
end if;
|
||||
pdi <= to_unsigned(data, pdi'length);
|
||||
pvi <= prdyo;
|
||||
end process;
|
||||
|
||||
tb_data : process (rst, clk, pvo)
|
||||
begin
|
||||
if rst = '1' then
|
||||
data_out <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if pvo = '1' then
|
||||
data_out <= pdo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user