- put TLB queries into pipeline

- removed TLB queries from Caches
- removed output register from TLB
- cleaned up
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1029 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/tb_mips_top.vhd

@@ -43,8 +43,6 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
 	constant WITH_TLB				: boolean := true;
-	constant ITLB_PIPE				: boolean := true;
-	constant DTLB_PIPE				: boolean := true;
 	constant KSEG_01_TRANSLATED		: boolean := true;
 	signal debug					: chip_debug_t;
 	signal tb_fin					: STD_LOGIC := '0';
@@ -284,9 +282,7 @@ uut: entity work.mips_top
 		icache_size			=> 256,		-- words
 		dcache_size			=> 256,		-- words
 		WITH_TLB			=> WITH_TLB,
-		TRANSLATE_KSEG0_1	=> KSEG_01_TRANSLATED,
-		ITLB_PIPE			=> ITLB_PIPE,
-		DTLB_PIPE			=> DTLB_PIPE
+		TRANSLATE_KSEG0_1	=> KSEG_01_TRANSLATED
 	)
 	PORT MAP
 	(