From 007c2ade027901d4600c59519d14e52c1b971c04 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 25 Aug 2013 18:41:04 +0000 Subject: [PATCH] - put TLB queries into pipeline - removed TLB queries from Caches - removed output register from TLB - cleaned up Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1029 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/sim/tb_mips_top.wdo | 40 +++++++++++++++---------------- lib/CPUs/MIPS/src/tb_mips_top.vhd | 6 +---- 2 files changed, 20 insertions(+), 26 deletions(-) diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo index 1d4de09..7079d2d 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -5,7 +5,7 @@ add wave -noupdate -format Literal /tb_mips_top/mem_area add wave -noupdate -format Logic /tb_mips_top/nmi add wave -noupdate -format Logic /tb_mips_top/rst add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/debug +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/debug add wave -noupdate -format Logic /tb_mips_top/cyc_o add wave -noupdate -format Logic /tb_mips_top/stb_o add wave -noupdate -format Logic /tb_mips_top/ack_i @@ -26,7 +26,6 @@ add wave -noupdate -format Literal /tb_mips_top/mem_area add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be add wave -noupdate -divider Busmaster add wave -noupdate -format Literal /tb_mips_top/mem_area add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_busmaster/clk @@ -151,6 +150,8 @@ add wave -noupdate -divider PC add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_in +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_i_tlb/query_out add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc add wave -noupdate -divider COP0 add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en @@ -185,7 +186,7 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage.exc add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.exc @@ -194,29 +195,31 @@ add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeli add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/wb_stage.exc add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ctrl_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ctrl_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/dtlb_qry_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/dtlb_qry_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/itlb_qry_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/itlb_qry_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/icache_qry_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/icache_qry_in add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem add wave -noupdate -divider I-Cache add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_busy_state add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_ctrl_state +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/query_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/query_out add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/debug add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/rst add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/clk add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_va add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_pa -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/single_read_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/addr add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/single_read_set add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/read_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/rdy -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/dout add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_req_rd add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tlb_query_out -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_icache/tlb_query_in add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/bus_din add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_rdy add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/bus_din_vld @@ -274,8 +277,12 @@ add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_hit add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/blk_entry_lo add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/pa add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/hit +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_i_tlb/vld_r +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_i_tlb/vaddr_reg add wave -noupdate -divider I-TLB-CAM add wave -noupdate -divider D-Cache +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/query_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/query_out add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy_state add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cache_ctrl_state add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_data_avail @@ -285,24 +292,16 @@ add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/i add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rst add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/clk add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_rd add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req_wr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_va add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_pa -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/tlb_query_out -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/tlb_query_in add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_set add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg_vld add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/single_read_reg add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/read_rdy add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/write_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/be add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_in add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/bus_din add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/bus_din_rdy @@ -392,7 +391,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_qry_entry_lo_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/reg_ctrl_entry_lo_raddr add wave -noupdate -format Literal -label reg_entry_lo_mem -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_d_tlb/inst_reg_entry_lo/reg_mem add wave -noupdate -divider D-TLB-CAM add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/rst @@ -439,7 +437,7 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_v add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/clear_count_rdy add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_i_tlb/inst_cam_va/over_write TreeUpdate [SetDefaultTree] -WaveRestoreCursors {Cursor {1330548448 ps} 0} +WaveRestoreCursors {Cursor {24310024 ps} 0} configure wave -namecolwidth 188 configure wave -valuecolwidth 154 configure wave -justifyvalue left @@ -453,4 +451,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {1499841793 ps} {1500008327 ps} +WaveRestoreZoom {24134231 ps} {24477503 ps} diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 023c1ae..66d4477 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -43,8 +43,6 @@ ARCHITECTURE behavior OF tb_mips_top IS constant SRAM_ADDR_WIDTH : integer := 17; -- bits constant FLASH_ADDR_WIDTH : integer := 17; -- bits constant WITH_TLB : boolean := true; - constant ITLB_PIPE : boolean := true; - constant DTLB_PIPE : boolean := true; constant KSEG_01_TRANSLATED : boolean := true; signal debug : chip_debug_t; signal tb_fin : STD_LOGIC := '0'; @@ -284,9 +282,7 @@ uut: entity work.mips_top icache_size => 256, -- words dcache_size => 256, -- words WITH_TLB => WITH_TLB, - TRANSLATE_KSEG0_1 => KSEG_01_TRANSLATED, - ITLB_PIPE => ITLB_PIPE, - DTLB_PIPE => DTLB_PIPE + TRANSLATE_KSEG0_1 => KSEG_01_TRANSLATED ) PORT MAP (