jens
4dbc4695fb
- bootloader_with_flash: fixed apperent bug with GPIO alignmentand masking git-svn-id: http://moon:8086/svn/mips@134 a8ebac50-d88d-4704-bea3-6648445a41b3
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/*
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* To change this license header, choose License Headers in Project Properties.
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* To change this template file, choose Tools | Templates
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* and open the template in the editor.
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*/
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/*
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* File: board.h
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* Author: jens
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*
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* Created on 8. Januar 2017, 11:33
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#define CPU_FREQ_HZ 50000000
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#define UART_STDIO 0
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#define UART_DEBUGGER 1
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// ---------------------------------------------------------
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// IRQs
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// ---------------------------------------------------------
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#define SYS_INT_SOFT_0 0
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#define SYS_INT_SOFT_1 1
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#define SYS_INT_TIMER 2
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#define SYS_INT_UART0 3
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#define SYS_INT_UART1 4
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#define SYS_INT_FLASH 5
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// ---------------------------------------------------------
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// Memory-mapped registers
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// ---------------------------------------------------------
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#ifndef SYS_IO_BASE
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#define SYS_IO_BASE 0xA0000000
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#endif
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#ifndef SDRAM_BASE
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#define SDRAM_BASE 0x40000000
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#endif
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#ifndef FLASH_BASE_IO
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#define FLASH_BASE_IO 0xA4000000
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#endif
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#ifndef FLASH_BASE_MEM
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#define FLASH_BASE_MEM 0x00000000
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#endif
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// Backwards compatibility
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#define SYS_FLASH_IO FLASH_BASE_IO
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#define SYS_FLASH_MEM FLASH_BASE_MEM
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// GPIO
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#define SYS_GPIO_0_BASE (SYS_IO_BASE + 0)
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#define SYS_GPIO_0_DATA (SYS_GPIO_0_BASE + 0)
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#define SYS_GPIO_0_DIR (SYS_GPIO_0_BASE + 4)
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#define GPIO_0_DFLT_DIR 0x00000000 // Inputs
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#define GPIO_0_DFLT_DATA 0x00000000
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#define GPIO_0_MASK_LED 0x000000FF
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#define GPIO_0_ALIGN_LED 0
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#define GPIO_0_MASK_DIP 0x0000000F
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#define GPIO_0_ALIGN_DIP 8
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#define GPIO_0_MASK_BTN 0x0000001F
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#define GPIO_0_ALIGN_BTN 24
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// RTC
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#define SYS_TIMER_USEC (SYS_IO_BASE + 0x8)
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#define SYS_TIMER_SEC (SYS_IO_BASE + 0xC)
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// TIMERs
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#define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18)
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#define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C)
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#define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20)
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#define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24)
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#define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28)
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#define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C)
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#define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30)
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#define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34)
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#define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38)
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#define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C)
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// UARTs
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#define SYS_UART_BIT_TX_HALFFULL 0x00000001
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#define SYS_UART_BIT_TX_FULL 0x00000002
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#define SYS_UART_BIT_RX_HALFFULL 0x00000004
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#define SYS_UART_BIT_RX_FULL 0x00000008
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#define SYS_UART_BIT_RX_AVAIL 0x00000010
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#define SYS_UART_BIT_TX_INTEN 0x00000020
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#define SYS_UART_BIT_RX_INTEN 0x00000040
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#define SYS_UART_BIT_TX_IRQ 0x00000100
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#define SYS_UART_BIT_RX_IRQ 0x00000200
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#define SYS_UART_DATA SYS_UART0_DATA
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#define SYS_UART_STAT SYS_UART0_STAT
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#define SYS_UART_BAUD SYS_UART0_BAUD
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#define SYS_UART0_DATA (SYS_IO_BASE + 0x10000)
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#define SYS_UART0_STAT (SYS_IO_BASE + 0x10004)
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#define SYS_UART0_BAUD (SYS_IO_BASE + 0x10008)
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#define SYS_UART1_DATA (SYS_IO_BASE + 0x30000)
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#define SYS_UART1_STAT (SYS_IO_BASE + 0x30004)
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#define SYS_UART1_BAUD (SYS_IO_BASE + 0x30008)
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// SPI
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#define SYS_SPI_STAT (SYS_IO_BASE + 0x20000)
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// Read
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#define SPI_STAT_CMDRDY (0x01)
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#define SPI_STAT_DINRDY (0x02)
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#define SPI_STAT_DOUTRDY (0x04)
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#define SPI_STAT_CMD_FIFO_FULL (0x0100)
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#define SPI_STAT_CMD_FIFO_EMPTY (0x0200)
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#define SPI_STAT_WRITE_FIFO_FULL (0x0400)
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#define SPI_STAT_WRITE_FIFO_EMPTY (0x0800)
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#define SPI_STAT_READ_FIFO_FULL (0x1000)
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#define SPI_STAT_READ_FIFO_EMPTY (0x2000)
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#define SPI_STAT_RX_VALID (0x4000)
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#define SPI_STAT_SPI_HOLD (0x8000)
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// Write
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#define SPI_STAT_COMMIT (1)
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#define SYS_SPI_XFER_SIZE (SYS_IO_BASE + 0x20004)
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#define SYS_SPI_DATA_SIZE (SYS_IO_BASE + 0x20008)
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#define SYS_SPI_DATA (SYS_IO_BASE + 0x2000C)
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#define SYS_SPI_CTRL (SYS_IO_BASE + 0x20010)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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