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- refactored

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- increased version

git-svn-id: http://moon:8086/svn/mips@177 a8ebac50-d88d-4704-bea3-6648445a41b3
This commit is contained in:
jens
2021-11-22 09:33:14 +00:00
parent 7ced3f1db1
commit c76849d2cc
1 changed files with 17 additions and 31 deletions
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src/bootloader/bootloader_with_flash.c
+17 -31
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@@ -111,31 +111,29 @@ void Exec_RE_at(void *pEntry)
}
#define MAX_IMG_SIZE (1024*1024) // bytes
#define SREC_BUFSIZE (1024)
int main(int argc, char *argv[])
{
uint8_t buf[1024];
uint8_t srec_buf[SREC_BUFSIZE];
srec_t srec;
int srec_state, i;
int srec_state;
uint32_t haddr = 0, result;
flash_t flash;
flash_img_hdr_t img_hdr = {0};
flash_img_hdr_t *pImg_hdr;
uint32_t img_size, block_sel;
uint32_t block_sel;
volatile uint32_t *pGPIO_DATA = (uint32_t*)SYS_GPIO_0_DATA;
volatile uint32_t *pGPIO_DIR = (uint32_t*)SYS_GPIO_0_DIR;
volatile uint8_t *pMem;
volatile uint32_t *pFlashIO = (uint32_t*)FLASH_BASE_IO; // Flash in uncached area
volatile uint32_t *pFlashMem = (uint32_t*)FLASH_BASE_MEM; // Flash in cached area
volatile uint32_t *ram32 = (uint32_t*)SDRAM_BASE;
uint32_t flash_offset;
*pGPIO_DIR = GPIO_0_DFLT_DIR;
*pGPIO_DATA = GPIO_0_DFLT_DATA;
block_sel = 0x7F & (uint32_t)((*pGPIO_DATA >> GPIO_0_ALIGN_DIP) & GPIO_0_MASK_DIP);
sputs("\nMIPS bootloader 2.0\n");
sputs("\n\nMIPS bootloader 2.01\n");
PrintCPUinfo();
// ----------------------------------------------------------
@@ -148,57 +146,45 @@ int main(int argc, char *argv[])
// Get flash offset by value of DIP-switch
flash_offset = flash_get_offset_by_blocknum(&flash, block_sel);
ram32 = (uint32_t*)(SDRAM_BASE);
pFlashIO = (uint32_t*)(SYS_FLASH_IO + flash_offset);
if (!(((*pGPIO_DATA & GPIO_0_MASK_BTN) >> GPIO_0_ALIGN_BTN) & 8))
if (!(((*pGPIO_DATA >> GPIO_0_ALIGN_BTN) & GPIO_0_MASK_BTN) & 2))
{
sputs("Loading image from flash at ");print_word(flash_offset);sputs("\n");
pImg_hdr = (flash_img_hdr_t*)pFlashIO;
if ((pImg_hdr->magic != MAGIC_EL) && (pImg_hdr->magic != MAGIC_EB))
{
sputs("\n\n");
sputs("Invalid image found at ");print_word(flash_offset); sputs(". Abort.\n");
return 1;
}
sputs("Image start flash : ");print_word(flash_offset);sputs("\n");
sputs("Image start RAM : ");print_word(pImg_hdr->target_base);sputs("\n");
sputs("Image size : ");print_word(pImg_hdr->img_size);sputs("\n");
sputs("Loading...");
ram32 = (uint32_t*)pImg_hdr->target_base;
img_size = pImg_hdr->img_size;
// Copy flash to RAM
// It's safe to use cached Flash,
// because D-Cache was invalidated during execution of start code
pFlashMem = (uint32_t*)pImg_hdr->img_base;
memcpy((uint32_t*)pImg_hdr->target_base, (uint32_t*)pImg_hdr->img_base, pImg_hdr->img_size);
for (i=0; i < img_size/4; i++)
ram32[i] = pFlashMem[i];
sputs("Booting from ");print_word(pImg_hdr->target_base);sputs("\n\n");
Exec_at((void*)ram32);
sputs("done\n");
Exec_at((void*)pImg_hdr->target_base);
}
else
{
sputs("\n\n");
sputs("Reading HEX-Record from UART..");
// Erase SDRAM
for (i=0; i < MAX_IMG_SIZE/4; i++)
ram32[i] = 0;
while(1)
{
sputs(".");
while(1)
{
result = srec_getline(buf);
srec_state = srec_decode(&srec, buf, result);
result = srec_getline(srec_buf);
srec_state = srec_decode(&srec, srec_buf, result);
switch (srec_state)
{
case srec_data:
result = -1;
if ((srec.addr + srec.size) > MAX_IMG_SIZE)
if ((srec.addr + srec.size) > (SDRAM_BASE + MAX_IMG_SIZE))
{
sputs("O");
break;