[mips/libsys]

- support different boards (Zwischenstand) git-svn-id: http://moon:8086/svn/mips@66 a8ebac50-d88d-4704-bea3-6648445a41b3
2017-01-08 12:42:55 +00:00
parent 1c58a2ce55
commit a67ef9649d
8 changed files with 418 additions and 266 deletions
@@ -0,0 +1,108 @@
+/*
+ * To change this license header, choose License Headers in Project Properties.
+ * To change this template file, choose Tools | Templates
+ * and open the template in the editor.
+ */
+
+/* 
+ * File:   board.h
+ * Author: jens
+ *
+ * Created on 8. Januar 2017, 11:33
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#define CPU_FREQ_HZ						50000000
+
+// ---------------------------------------------------------
+// IRQs
+// ---------------------------------------------------------
+#define	SYS_INT_TIMER					2
+#define	SYS_INT_UART0					3
+#define	SYS_INT_UART1					4
+#define	SYS_INT_FLASH					5
+#define	SYS_INT_SOFT_1					1
+#define	SYS_INT_SOFT_0					0
+
+// ---------------------------------------------------------
+// Memory-mapped registers
+// ---------------------------------------------------------
+#ifndef SYS_IO_BASE
+#define SYS_IO_BASE			0xA0000000
+#endif
+#ifndef SDRAM_BASE
+#define SDRAM_BASE			0x40000000
+#endif
+#ifndef FLASH_BASE_IO
+#define FLASH_BASE_IO		0xA4000000
+#endif
+#ifndef FLASH_BASE_MEM
+#define FLASH_BASE_MEM		0x00000000
+#endif
+
+// Backwards compatibility
+#define SYS_FLASH_IO		FLASH_BASE_IO
+#define SYS_FLASH_MEM		FLASH_BASE_MEM
+
+// GPIO
+#define	SYS_GPIO_0_BASE					(SYS_IO_BASE + 0)
+#define	SYS_GPIO_0_DATA					(SYS_GPIO_0_BASE + 0)
+#define	SYS_GPIO_0_DIR					(SYS_GPIO_0_BASE + 4)
+
+#define	GPIO_0_DFLT_DIR					0x00000000		// Inputs
+#define	GPIO_0_DFLT_DATA				0x00000000
+
+#define	GPIO_0_MASK_LED					0x000000FF
+#define	GPIO_0_ALIGN_LED				0
+
+// RTC
+#define	SYS_TIMER_USEC					(SYS_IO_BASE + 0x8)
+#define	SYS_TIMER_SEC					(SYS_IO_BASE + 0xC)
+
+// TIMERs
+#define	SYS_ITIM_CTRL					(SYS_IO_BASE + 0x18)
+#define	SYS_ITIM_STAT					(SYS_IO_BASE + 0x1C)
+#define	SYS_ITIM0_CNT					(SYS_IO_BASE + 0x20)
+#define	SYS_ITIM1_CNT					(SYS_IO_BASE + 0x24)
+#define	SYS_ITIM2_CNT					(SYS_IO_BASE + 0x28)
+#define	SYS_ITIM3_CNT					(SYS_IO_BASE + 0x2C)
+#define	SYS_ITIM0_CMP					(SYS_IO_BASE + 0x30)
+#define	SYS_ITIM1_CMP					(SYS_IO_BASE + 0x34)
+#define	SYS_ITIM2_CMP					(SYS_IO_BASE + 0x38)
+#define	SYS_ITIM3_CMP					(SYS_IO_BASE + 0x3C)
+
+// UARTs
+#define SYS_UART_BIT_TX_HALFFULL		0x00000001
+#define SYS_UART_BIT_TX_FULL			0x00000002
+#define SYS_UART_BIT_RX_HALFFULL		0x00000004
+#define SYS_UART_BIT_RX_FULL			0x00000008
+#define SYS_UART_BIT_RX_AVAIL			0x00000010
+#define SYS_UART_BIT_TX_INTEN			0x00000020
+#define SYS_UART_BIT_RX_INTEN			0x00000040
+#define SYS_UART_BIT_TX_IRQ				0x00000100
+#define SYS_UART_BIT_RX_IRQ				0x00000200
+#define	SYS_UART_DATA					SYS_UART0_DATA
+#define	SYS_UART_STAT					SYS_UART0_STAT
+#define	SYS_UART_BAUD					SYS_UART0_BAUD
+#define	SYS_UART0_DATA					(SYS_IO_BASE + 0x10000)
+#define	SYS_UART0_STAT					(SYS_IO_BASE + 0x10004)
+#define	SYS_UART0_BAUD					(SYS_IO_BASE + 0x10008)
+#define	SYS_UART1_DATA					(SYS_IO_BASE + 0x10100)
+#define	SYS_UART1_STAT					(SYS_IO_BASE + 0x10104)
+#define	SYS_UART1_BAUD					(SYS_IO_BASE + 0x10108)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+