[mips/libsys]
- support different boards (Zwischenstand) git-svn-id: http://moon:8086/svn/mips@66 a8ebac50-d88d-4704-bea3-6648445a41b3
This commit is contained in:
+5
-4
@@ -1,5 +1,6 @@
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ENDIAN='big'
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BOARD=ml402
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ifeq ($(TLB),yes)
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SPECNAME=specs_tlb
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else
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@@ -8,10 +9,10 @@ endif
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ifeq ($(ENDIAN), 'big')
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ENDIAN_FLAGS=-EB
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CFLAGS=$(ENDIAN_FLAGS) -specs=specs/eb/$(SPECNAME) -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
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CFLAGS=$(ENDIAN_FLAGS) -specs=specs/eb/$(SPECNAME) -msoft-float -O2 -march=r3000 -I. -Ilibsys -Ilibsys/boards/$(BOARD) -Wl,-M
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else
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ENDIAN_FLAGS=-EL
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CFLAGS=$(ENDIAN_FLAGS) -specs=specs/$(SPECNAME) -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
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CFLAGS=$(ENDIAN_FLAGS) -specs=specs/$(SPECNAME) -msoft-float -O2 -march=r3000 -I. -Ilibsys -Ilibsys/boards/$(BOARD) -Wl,-M
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endif
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ifeq ($(TLB),yes)
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@@ -44,7 +45,7 @@ all: $(PROG)
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libsys.a:
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$(MAKE) -C libsys
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$(MAKE) -C libsys BOARD=$(BOARD)
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libsys_sim.a:
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$(MAKE) -C libsys
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@@ -5,7 +5,6 @@
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#include <ctype.h>
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#include <time.h>
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#define CPU_FREQ_HZ 100000000
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#include "libsys.h"
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#include "crc32.h"
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+8
-4
@@ -1,5 +1,9 @@
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# environment vaiables read:
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# BOARD
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ENDIAN_FLAGS=-EL
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CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M
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CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M -Iboards/$(BOARD)
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ifeq ($(TLB),yes)
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CFLAGS+=-DSYS_IO_BASE=0xAC000000 -DSDRAM_BASE=0x80000000 -DFLASH_BASE_IO=0xA4000000 -DFLASH_BASE_MEM=0x88000000
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@@ -18,10 +22,10 @@ FLASHGEN=flashgen
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SRCS=libsys.c xcpt.c syscalls.c irq.c mips_dbg.c mips_dis.c mips_gfx.c mips_ps2.c gpio.c
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OBJS=libsys.o xcpt.o syscalls.o irq.o mips_dbg.o mips_dis.o mips_gfx.o mips_ps2.o gpio.o
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.PHONY : libsys.a libsys_sim.a
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.PHONY : libsys.a
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all: libsys.a libsys_sim.a
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$(MAKE) -C eb
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all: libsys.a
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$(MAKE) -C eb BOARD=$(BOARD)
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$(OBJS): $(SRCS)
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$(CC) $(CFLAGS) -G 0 -c $(SRCS)
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@@ -0,0 +1,108 @@
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/*
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* To change this license header, choose License Headers in Project Properties.
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* To change this template file, choose Tools | Templates
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* and open the template in the editor.
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*/
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/*
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* File: board.h
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* Author: jens
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*
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* Created on 8. Januar 2017, 11:33
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#define CPU_FREQ_HZ 50000000
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// ---------------------------------------------------------
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// IRQs
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// ---------------------------------------------------------
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#define SYS_INT_TIMER 2
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#define SYS_INT_UART0 3
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#define SYS_INT_UART1 4
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#define SYS_INT_FLASH 5
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#define SYS_INT_SOFT_1 1
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#define SYS_INT_SOFT_0 0
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// ---------------------------------------------------------
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// Memory-mapped registers
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// ---------------------------------------------------------
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#ifndef SYS_IO_BASE
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#define SYS_IO_BASE 0xA0000000
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#endif
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#ifndef SDRAM_BASE
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#define SDRAM_BASE 0x40000000
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#endif
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#ifndef FLASH_BASE_IO
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#define FLASH_BASE_IO 0xA4000000
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#endif
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#ifndef FLASH_BASE_MEM
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#define FLASH_BASE_MEM 0x00000000
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#endif
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// Backwards compatibility
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#define SYS_FLASH_IO FLASH_BASE_IO
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#define SYS_FLASH_MEM FLASH_BASE_MEM
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// GPIO
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#define SYS_GPIO_0_BASE (SYS_IO_BASE + 0)
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#define SYS_GPIO_0_DATA (SYS_GPIO_0_BASE + 0)
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#define SYS_GPIO_0_DIR (SYS_GPIO_0_BASE + 4)
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#define GPIO_0_DFLT_DIR 0x00000000 // Inputs
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#define GPIO_0_DFLT_DATA 0x00000000
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#define GPIO_0_MASK_LED 0x000000FF
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#define GPIO_0_ALIGN_LED 0
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// RTC
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#define SYS_TIMER_USEC (SYS_IO_BASE + 0x8)
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#define SYS_TIMER_SEC (SYS_IO_BASE + 0xC)
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// TIMERs
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#define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18)
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#define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C)
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#define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20)
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#define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24)
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#define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28)
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#define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C)
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#define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30)
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#define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34)
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#define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38)
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#define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C)
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// UARTs
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#define SYS_UART_BIT_TX_HALFFULL 0x00000001
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#define SYS_UART_BIT_TX_FULL 0x00000002
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#define SYS_UART_BIT_RX_HALFFULL 0x00000004
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#define SYS_UART_BIT_RX_FULL 0x00000008
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#define SYS_UART_BIT_RX_AVAIL 0x00000010
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#define SYS_UART_BIT_TX_INTEN 0x00000020
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#define SYS_UART_BIT_RX_INTEN 0x00000040
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#define SYS_UART_BIT_TX_IRQ 0x00000100
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#define SYS_UART_BIT_RX_IRQ 0x00000200
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#define SYS_UART_DATA SYS_UART0_DATA
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#define SYS_UART_STAT SYS_UART0_STAT
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#define SYS_UART_BAUD SYS_UART0_BAUD
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#define SYS_UART0_DATA (SYS_IO_BASE + 0x10000)
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#define SYS_UART0_STAT (SYS_IO_BASE + 0x10004)
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#define SYS_UART0_BAUD (SYS_IO_BASE + 0x10008)
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#define SYS_UART1_DATA (SYS_IO_BASE + 0x10100)
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#define SYS_UART1_STAT (SYS_IO_BASE + 0x10104)
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#define SYS_UART1_BAUD (SYS_IO_BASE + 0x10108)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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@@ -0,0 +1,255 @@
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/*
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* To change this license header, choose License Headers in Project Properties.
|
||||
* To change this template file, choose Tools | Templates
|
||||
* and open the template in the editor.
|
||||
*/
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/*
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* File: board.h
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* Author: jens
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*
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* Created on 8. Januar 2017, 11:33
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#define CPU_FREQ_HZ 100000000
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// ---------------------------------------------------------
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// IRQs
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// ---------------------------------------------------------
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#define SYS_INT_TIMER 7
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#define SYS_INT_PS2 6
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#define SYS_INT_EMAC 6
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#define SYS_INT_VGA 5
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#define SYS_INT_AC97 5
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#define SYS_INT_USB 4
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#define SYS_INT_UART 3
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#define SYS_INT_DBG 2
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#define SYS_INT_SOFT_1 1
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#define SYS_INT_SOFT_0 0
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// ---------------------------------------------------------
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// Memory-mapped registers
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// ---------------------------------------------------------
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#ifndef SYS_IO_BASE
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#define SYS_IO_BASE 0xA0000000
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#endif
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#ifndef SDRAM_BASE
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#define SDRAM_BASE 0x40000000
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#endif
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#ifndef FLASH_BASE_IO
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#define FLASH_BASE_IO 0xA4000000
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#endif
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#ifndef FLASH_BASE_MEM
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#define FLASH_BASE_MEM 0x00000000
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#endif
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// Backwards compatibility
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#define SYS_FLASH_IO FLASH_BASE_IO
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#define SYS_FLASH_MEM FLASH_BASE_MEM
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// GPIO
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#define SYS_GPIO_0_BASE (SYS_IO_BASE + 0)
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#define SYS_GPIO_0_DATA (SYS_GPIO_0_BASE + 0)
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#define SYS_GPIO_0_DIR (SYS_GPIO_0_BASE + 4)
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#define GPIO_0_DFLT_DIR 0x00000000 // Inputs
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#define GPIO_0_DFLT_DATA 0x00000000
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#define GPIO_0_MASK_LED 0x000001FF
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#define GPIO_0_ALIGN_LED 0
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#define GPIO_0_MASK_USB 0x00000003
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#define GPIO_0_ALIGN_USB 12
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#define GPIO_0_USB_RST 0x00000001
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#define GPIO_0_USB_INTEN 0x00000002
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#define GPIO_0_MASK_AC97 0x00000001
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#define GPIO_0_ALIGN_AC97 15
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#define GPIO_0_AC97_INTEN 0x00000001
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#define GPIO_0_MASK_DIP 0x000000FF
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#define GPIO_0_ALIGN_DIP 16
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#define GPIO_0_MASK_BTN 0x0000001F
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#define GPIO_0_ALIGN_BTN 24
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#define GPIO_0_MASK_MDIO 0x00000007
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#define GPIO_0_ALIGN_MDIO 29
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#define GPIO_0_MDIO_INTEN 0x00000001 // ToDo: better grouping
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#define GPIO_0_MDIO_RST 0x00000001
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#define GPIO_0_MDIO_MDC 0x00000002
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#define GPIO_0_MDIO_MDIO 0x00000004
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// RTC
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#define SYS_TIMER_USEC (SYS_IO_BASE + 0x8)
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#define SYS_TIMER_SEC (SYS_IO_BASE + 0xC)
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// TIMERs
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#define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18)
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#define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C)
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#define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20)
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#define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24)
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#define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28)
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#define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C)
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#define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30)
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#define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34)
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#define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38)
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#define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C)
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// UARTs
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#define SYS_UART_BIT_TX_HALFFULL 0x00000001
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#define SYS_UART_BIT_TX_FULL 0x00000002
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#define SYS_UART_BIT_RX_HALFFULL 0x00000004
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#define SYS_UART_BIT_RX_FULL 0x00000008
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#define SYS_UART_BIT_RX_AVAIL 0x00000010
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#define SYS_UART_BIT_TX_INTEN 0x00000020
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#define SYS_UART_BIT_RX_INTEN 0x00000040
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#define SYS_UART_BIT_TX_IRQ 0x00000100
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#define SYS_UART_BIT_RX_IRQ 0x00000200
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#define SYS_UART_DATA SYS_UART0_DATA
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#define SYS_UART_STAT SYS_UART0_STAT
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#define SYS_UART_BAUD SYS_UART0_BAUD
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#define SYS_UART0_DATA (SYS_IO_BASE + 0x10000)
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#define SYS_UART0_STAT (SYS_IO_BASE + 0x10004)
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#define SYS_UART0_BAUD (SYS_IO_BASE + 0x10008)
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#define SYS_UART1_DATA (SYS_IO_BASE + 0x10100)
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#define SYS_UART1_STAT (SYS_IO_BASE + 0x10104)
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#define SYS_UART1_BAUD (SYS_IO_BASE + 0x10108)
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// PS2s
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#define SYS_PS2_BIT_TX_EMPTY 0x00000001
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#define SYS_PS2_BIT_RX_AVAIL 0x00000004
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#define SYS_PS2_BIT_PIN_CLOCK 0x00000008
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#define SYS_PS2_BIT_PIN_DATA 0x00000010
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#define SYS_PS2_BIT_TX_INTEN 0x00000020
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#define SYS_PS2_BIT_RX_INTEN 0x00000040
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#define SYS_PS2_BIT_TX_IRQ 0x00000100
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#define SYS_PS2_BIT_RX_IRQ 0x00000200
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#define SYS_PS2_BIT_RX_ERR_PAR 0x00000800
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#define SYS_PS2_BIT_RX_ERR_FLAG 0x00008000
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#define SYS_PS2_0_DATA (SYS_IO_BASE + 0x10200)
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#define SYS_PS2_0_STAT (SYS_IO_BASE + 0x10204)
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#define SYS_PS2_1_DATA (SYS_IO_BASE + 0x10300)
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#define SYS_PS2_1_STAT (SYS_IO_BASE + 0x10304)
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// USB
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#define SYS_USB_DATA (SYS_IO_BASE + 0x20000)
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#define SYS_USB_MBX (SYS_IO_BASE + 0x20004)
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#define SYS_USB_ADDR (SYS_IO_BASE + 0x20008)
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#define SYS_USB_STATUS (SYS_IO_BASE + 0x2000C)
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// VGA
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#define SYS_VGA_CTRL (SYS_IO_BASE + 0x30000) // R/W
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#define SYS_VGA_BIT_CGRDY 0x00000001 // RO
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#define SYS_VGA_BIT_MSTEN 0x00000002 // R/W
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#define SYS_VGA_BIT_BUFCHG_INTEN 0x00000004 // RO
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#define SYS_VGA_BIT_BUFCHG_FLAG 0x00000008 // RO
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#define SYS_VGA_BIT_CLRSCR 0x00000010 // WO
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#define SYS_VGA_BIT_CLRLINE 0x00000020 // WO
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#define SYS_VGA_BIT_BLIT_REQ 0x00000100 // R/W
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#define SYS_VGA_BIT_BLIT_BSY 0x00000100 // R/W
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#define SYS_VGA_BIT_BLIT_FIN 0x00000200 // R/W
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#define SYS_VGA_BIT_BLIT_FIN_ACK 0x00000200 // R/W
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#define SYS_VGA_BIT_BLIT_FIN_INTEN 0x00000400 // R/W
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#define SYS_VGA_BIT_BLIT_EMPTY 0x00000800 // R/W
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#define SYS_VGA_BIT_BLIT_EMPTY_ACK 0x00000800 // R/W
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#define SYS_VGA_BIT_BLIT_EMPTY_INTEN 0x00001000 // R/W
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#define SYS_VGA_BIT_BLIT_OP_CONSTCOL 0x00010000 // R/W
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#define SYS_VGA_BIT_BLIT_ACTIVE 0x80000000 // RO
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#define SYS_VGA_ASCII (SYS_IO_BASE + 0x30004) // R/W
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#define SYS_VGA_POSX (SYS_IO_BASE + 0x30008) // R/W
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#define SYS_VGA_POSY (SYS_IO_BASE + 0x3000C) // R/W
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#define SYS_VGA_CGCOL (SYS_IO_BASE + 0x30010) // R/W
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#define SYS_VGA_RES (SYS_IO_BASE + 0x30014) // RO
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#define SYS_VGA_FB_FRONT (SYS_IO_BASE + 0x30018) // R/W
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#define SYS_VGA_FB_BACK (SYS_IO_BASE + 0x3001C) // R/W
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#define SYS_VGA_BLIT_SRC0_ADDR (SYS_IO_BASE + 0x30020) // R/W
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#define SYS_VGA_BLIT_SRC0_DIMX (SYS_IO_BASE + 0x30024) // R/W
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#define SYS_VGA_BLIT_SRC1_ADDR (SYS_IO_BASE + 0x30030) // R/W
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#define SYS_VGA_BLIT_SRC1_DIMX (SYS_IO_BASE + 0x30034) // R/W
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#define SYS_VGA_BLIT_DST_ADDR (SYS_IO_BASE + 0x30040) // R/W
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#define SYS_VGA_BLIT_DST_DIMX (SYS_IO_BASE + 0x30044) // R/W
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#define SYS_VGA_BLIT_NX (SYS_IO_BASE + 0x30050) // R/W
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#define SYS_VGA_BLIT_NY (SYS_IO_BASE + 0x30054) // R/W
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#define SYS_VGA_BLIT_COLOR (SYS_IO_BASE + 0x30058) // R/W
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// AC'97
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#define SYS_AC97_STAT (SYS_IO_BASE + 0x40000)
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#define SYS_AC97_CTRL (SYS_IO_BASE + 0x40000)
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#define SYS_AC97_ACSTAT (SYS_IO_BASE + 0x40400)
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#define SYS_AC97_ACCTRL (SYS_IO_BASE + 0x40600)
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#define SYS_AC97_PCM (SYS_IO_BASE + 0x40800)
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#define SYS_AC97_WAVIN SYS_AC97_PCM
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#define SYS_AC97_WAVOUT SYS_AC97_PCM
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// Ethernet MAC
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#define SYS_EMAC_RX_CTRL (SYS_IO_BASE + 0x50000)
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#define EMAC_RX_CTRL_RESET (1 << 31)
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#define EMAC_RX_CTRL_GIGABIT (1 << 30)
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#define EMAC_RX_CTRL_FCS_CHECK (1 << 29)
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#define EMAC_RX_CTRL_PROMISCIOUS (1 << 23)
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#define EMAC_RX_CTRL_PKT_REQ (1 << 17)
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#define EMAC_RX_CTRL_PKT_FREE (1 << 16)
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||||
#define EMAC_RX_CTRL_INTEN (1 << 4)
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||||
|
||||
#define SYS_EMAC_RX_STAT SYS_EMAC_RX_CTRL
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||||
#define EMAC_RX_STAT_RESET (1 << 31)
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||||
#define EMAC_RX_STAT_GIGABIT (1 << 30)
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||||
#define EMAC_RX_STAT_FCS_CHECK (1 << 29)
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||||
#define EMAC_RX_STAT_PROMISCIOUS (1 << 23)
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||||
#define EMAC_RX_STAT_PKT_BCAST (1 << 19)
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||||
#define EMAC_RX_STAT_PKT_MACOK (1 << 18)
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||||
#define EMAC_RX_STAT_PKT_VALID (1 << 17)
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||||
#define EMAC_RX_STAT_PKT_AVAIL (1 << 16)
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||||
#define EMAC_RX_STAT_INTEN (1 << 4)
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||||
|
||||
#define SYS_EMAC_RX_SIZE (SYS_IO_BASE + 0x50004)
|
||||
|
||||
#define SYS_EMAC_TX_CTRL (SYS_IO_BASE + 0x50008)
|
||||
#define EMAC_TX_CTRL_RESET (1 << 31)
|
||||
#define EMAC_TX_CTRL_GIGABIT (1 << 30)
|
||||
#define EMAC_TX_CTRL_FCS_APPEND (1 << 29)
|
||||
#define EMAC_TX_CTRL_PKT_ALLOC (1 << 17)
|
||||
#define EMAC_TX_CTRL_PKT_COMMIT (1 << 16)
|
||||
#define EMAC_TX_CTRL_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_TX_STAT SYS_EMAC_TX_CTRL
|
||||
#define EMAC_TX_STAT_RESET (1 << 31)
|
||||
#define EMAC_TX_STAT_GIGABIT (1 << 30)
|
||||
#define EMAC_TX_STAT_FCS_APPEND (1 << 29)
|
||||
#define EMAC_TX_STAT_PKT_DONE (1 << 24)
|
||||
#define EMAC_TX_STAT_PKT_ALLOC_BSY (1 << 17)
|
||||
#define EMAC_TX_STAT_PKT_ARMED (1 << 16)
|
||||
#define EMAC_TX_STAT_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_TX_SIZE (SYS_IO_BASE + 0x5000C)
|
||||
#define SYS_EMAC_MADDR (SYS_IO_BASE + 0x50018)
|
||||
#define SYS_EMAC_MADDR_0 SYS_EMAC_MADDR_0
|
||||
#define SYS_EMAC_MADDR_1 (SYS_IO_BASE + 0x5001C)
|
||||
|
||||
#define SYS_EMAC_DATA (SYS_IO_BASE + 0x58000)
|
||||
#define SYS_EMAC_RX_DATA SYS_EMAC_DATA
|
||||
#define SYS_EMAC_TX_DATA SYS_EMAC_DATA
|
||||
#define SYS_EMAC_DATA_CACHED (SYS_IO_BASE + 0x10008000)
|
||||
|
||||
// Sync. SRAM
|
||||
#define SYS_SSRAM_IO 0xA8000000
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
||||
@@ -1,5 +1,8 @@
|
||||
# environment vaiables read:
|
||||
# BOARD
|
||||
|
||||
ENDIAN_FLAGS=-EB
|
||||
CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I../ -Wl,-M
|
||||
CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I../ -I../boards/$(BOARD) -Wl,-M
|
||||
|
||||
ifeq ($(TLB),yes)
|
||||
CFLAGS+=-DSYS_IO_BASE=0xAC000000 -DSDRAM_BASE=0x80000000 -DFLASH_BASE_IO=0xA4000000 -DFLASH_BASE_MEM=0x88000000
|
||||
@@ -18,11 +21,11 @@ FLASHGEN=flashgen
|
||||
SRCS=../libsys.c ../xcpt.c ../syscalls.c ../irq.c ../mips_dbg.c ../mips_dis.c ../mips_gfx.c ../mips_ps2.c ../gpio.c
|
||||
OBJS=libsys.o xcpt.o syscalls.o irq.o mips_dbg.o mips_dis.o mips_gfx.o mips_ps2.o gpio.o
|
||||
|
||||
OBJS_SIM=libsys_sim.o xcpt.o syscalls.o irq.o gpio.o
|
||||
OBJS_SIM=xcpt.o syscalls.o irq.o gpio.o
|
||||
|
||||
.PHONY : libsys.a libsys_sim.a
|
||||
.PHONY : libsys.a
|
||||
|
||||
all: libsys.a libsys_sim.a
|
||||
all: libsys.a
|
||||
|
||||
$(OBJS): $(SRCS)
|
||||
$(CC) $(CFLAGS) -G 0 -c $(SRCS)
|
||||
|
||||
+31
-18
@@ -61,6 +61,18 @@ enum
|
||||
PORT_OUT_VGA
|
||||
};
|
||||
|
||||
#define CALC_BAUD(b) \
|
||||
((uint32_t)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1);
|
||||
|
||||
void UART0_setbaud(uint32_t baudrate)
|
||||
{
|
||||
*((uint32_t*)SYS_UART0_BAUD) = CALC_BAUD(baudrate);
|
||||
}
|
||||
|
||||
void UART1_setbaud(uint32_t baudrate)
|
||||
{
|
||||
*((uint32_t*)SYS_UART1_BAUD) = CALC_BAUD(baudrate);
|
||||
}
|
||||
|
||||
uint32_t GetPort(int file)
|
||||
{
|
||||
@@ -318,7 +330,7 @@ static const libsys_key_entry_t __keymap_german[] =
|
||||
{0x32, 'b', 'B', 'b'},
|
||||
{0x21, 'c', 'C', 'c'},
|
||||
{0x23, 'd', 'D', 'd'},
|
||||
{0x24, 'e', 'E', '�'},
|
||||
{0x24, 'e', 'E', '€'},
|
||||
{0x2b, 'f', 'F', 'f'},
|
||||
{0x34, 'g', 'G', 'g'},
|
||||
{0x33, 'h', 'H', 'h'},
|
||||
@@ -326,7 +338,7 @@ static const libsys_key_entry_t __keymap_german[] =
|
||||
{0x3b, 'j', 'J', 'j'},
|
||||
{0x42, 'k', 'K', 'k'},
|
||||
{0x4b, 'l', 'L', 'l'},
|
||||
{0x3a, 'm', 'M', '�'},
|
||||
{0x3a, 'm', 'M', 'µ'},
|
||||
{0x31, 'n', 'N', 'n'},
|
||||
{0x44, 'o', 'O', 'o'},
|
||||
{0x4d, 'p', 'P', 'p'},
|
||||
@@ -342,7 +354,7 @@ static const libsys_key_entry_t __keymap_german[] =
|
||||
{0x35, 'z', 'Z', 'z'},
|
||||
{0x16, '1', '!', '1'},
|
||||
{0x1e, '2', '"', '2'},
|
||||
{0x26, '3', '�', '3'},
|
||||
{0x26, '3', '§', '3'},
|
||||
{0x25, '4', '$', '4'},
|
||||
{0x2e, '5', '%', '5'},
|
||||
{0x36, '6', '&', '6'},
|
||||
@@ -350,21 +362,22 @@ static const libsys_key_entry_t __keymap_german[] =
|
||||
{0x3e, '8', '(', '['},
|
||||
{0x46, '9', ')', ']'},
|
||||
{0x45, '0', '=', '}'},
|
||||
{0x4e, '�', '?', '\\'},
|
||||
{0x4e, 'ß', '?', '\\'},
|
||||
{0x29, ' ', ' ', ' '},
|
||||
{0x41, ',', ';', ','},
|
||||
{0x49, '.', ':', '.'},
|
||||
{0x4a, '-', '_', '-'},
|
||||
{0x52, '�', '�', '�'},
|
||||
{0x4c, '�', '�', '�'},
|
||||
{0x54, '�', '�', '�'},
|
||||
{0x52, 'ä', 'Ä', 'ä'},
|
||||
{0x4c, 'ö', 'Ö', 'ö'},
|
||||
{0x54, 'ü', 'Ü', 'ü'},
|
||||
{0x5a, '\n', '\n', '\n'}, //RETURN
|
||||
{0x5b, '+', '*', '~'},
|
||||
{0x5d, '#', '\'', '#'},
|
||||
{0x0e, '^', '�', '^'},
|
||||
{0x0e, '^', '°', '^'},
|
||||
{0x61, '<', '>', '|'},
|
||||
{0x66, '\b', '\b', '\b'},
|
||||
{0} //sentinel
|
||||
|
||||
};
|
||||
|
||||
static char __findkey(char scancode, int mode)
|
||||
@@ -533,27 +546,27 @@ void cg_writechar(vga_if_t *pIF, char c)
|
||||
// Output translation
|
||||
switch(c)
|
||||
{
|
||||
case '�':
|
||||
case 'Ä':
|
||||
code = 196;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'ä':
|
||||
code = 228;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'Ö':
|
||||
code = 214;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'ö':
|
||||
code = 246;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'Ü':
|
||||
code = 220;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'ü':
|
||||
code = 252;
|
||||
break;
|
||||
|
||||
@@ -561,19 +574,19 @@ void cg_writechar(vga_if_t *pIF, char c)
|
||||
code = 230;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case '§':
|
||||
code = 167;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'ß':
|
||||
code = 223;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case '°':
|
||||
code = 176;
|
||||
break;
|
||||
|
||||
case '�':
|
||||
case 'µ':
|
||||
code = 181;
|
||||
break;
|
||||
|
||||
|
||||
+4
-235
@@ -2,6 +2,7 @@
|
||||
#define LIBSYS_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <board.h>
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// Types
|
||||
@@ -14,230 +15,6 @@
|
||||
|
||||
#define IS_ERROR(e) ((e & LSYS_ERR_BASE) == LSYS_ERR_BASE)
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// IRQs
|
||||
// ---------------------------------------------------------
|
||||
#define SYS_INT_TIMER 7
|
||||
#define SYS_INT_PS2 6
|
||||
#define SYS_INT_EMAC 6
|
||||
#define SYS_INT_VGA 5
|
||||
#define SYS_INT_AC97 5
|
||||
#define SYS_INT_USB 4
|
||||
#define SYS_INT_UART 3
|
||||
#define SYS_INT_DBG 2
|
||||
#define SYS_INT_SOFT_1 1
|
||||
#define SYS_INT_SOFT_0 0
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// Memory-mapped registers
|
||||
// ---------------------------------------------------------
|
||||
#ifndef SYS_IO_BASE
|
||||
#define SYS_IO_BASE 0xA0000000
|
||||
#endif
|
||||
#ifndef SDRAM_BASE
|
||||
#define SDRAM_BASE 0x40000000
|
||||
#endif
|
||||
#ifndef FLASH_BASE_IO
|
||||
#define FLASH_BASE_IO 0xA4000000
|
||||
#endif
|
||||
#ifndef FLASH_BASE_MEM
|
||||
#define FLASH_BASE_MEM 0x00000000
|
||||
#endif
|
||||
|
||||
// Backwards compatibility
|
||||
#define SYS_FLASH_IO FLASH_BASE_IO
|
||||
#define SYS_FLASH_MEM FLASH_BASE_MEM
|
||||
|
||||
// GPIO
|
||||
#define SYS_GPIO_0_BASE (SYS_IO_BASE + 0)
|
||||
#define SYS_GPIO_0_DATA (SYS_GPIO_0_BASE + 0)
|
||||
#define SYS_GPIO_0_DIR (SYS_GPIO_0_BASE + 4)
|
||||
|
||||
#define GPIO_0_DFLT_DIR 0x00000000 // Inputs
|
||||
#define GPIO_0_DFLT_DATA 0x00000000
|
||||
|
||||
#define GPIO_0_MASK_LED 0x000001FF
|
||||
#define GPIO_0_ALIGN_LED 0
|
||||
|
||||
#define GPIO_0_MASK_USB 0x00000003
|
||||
#define GPIO_0_ALIGN_USB 12
|
||||
#define GPIO_0_USB_RST 0x00000001
|
||||
#define GPIO_0_USB_INTEN 0x00000002
|
||||
|
||||
#define GPIO_0_MASK_AC97 0x00000001
|
||||
#define GPIO_0_ALIGN_AC97 15
|
||||
#define GPIO_0_AC97_INTEN 0x00000001
|
||||
|
||||
#define GPIO_0_MASK_DIP 0x000000FF
|
||||
#define GPIO_0_ALIGN_DIP 16
|
||||
|
||||
#define GPIO_0_MASK_BTN 0x0000001F
|
||||
#define GPIO_0_ALIGN_BTN 24
|
||||
|
||||
#define GPIO_0_MASK_MDIO 0x00000007
|
||||
#define GPIO_0_ALIGN_MDIO 29
|
||||
#define GPIO_0_MDIO_INTEN 0x00000001 // ToDo: better grouping
|
||||
#define GPIO_0_MDIO_RST 0x00000001
|
||||
#define GPIO_0_MDIO_MDC 0x00000002
|
||||
#define GPIO_0_MDIO_MDIO 0x00000004
|
||||
|
||||
|
||||
// RTC
|
||||
#define SYS_TIMER_USEC (SYS_IO_BASE + 0x8)
|
||||
#define SYS_TIMER_SEC (SYS_IO_BASE + 0xC)
|
||||
|
||||
// TIMERs
|
||||
#define SYS_ITIM_CTRL (SYS_IO_BASE + 0x18)
|
||||
#define SYS_ITIM_STAT (SYS_IO_BASE + 0x1C)
|
||||
#define SYS_ITIM0_CNT (SYS_IO_BASE + 0x20)
|
||||
#define SYS_ITIM1_CNT (SYS_IO_BASE + 0x24)
|
||||
#define SYS_ITIM2_CNT (SYS_IO_BASE + 0x28)
|
||||
#define SYS_ITIM3_CNT (SYS_IO_BASE + 0x2C)
|
||||
#define SYS_ITIM0_CMP (SYS_IO_BASE + 0x30)
|
||||
#define SYS_ITIM1_CMP (SYS_IO_BASE + 0x34)
|
||||
#define SYS_ITIM2_CMP (SYS_IO_BASE + 0x38)
|
||||
#define SYS_ITIM3_CMP (SYS_IO_BASE + 0x3C)
|
||||
|
||||
// UARTs
|
||||
#define SYS_UART_BIT_TX_HALFFULL 0x00000001
|
||||
#define SYS_UART_BIT_TX_FULL 0x00000002
|
||||
#define SYS_UART_BIT_RX_HALFFULL 0x00000004
|
||||
#define SYS_UART_BIT_RX_FULL 0x00000008
|
||||
#define SYS_UART_BIT_RX_AVAIL 0x00000010
|
||||
#define SYS_UART_BIT_TX_INTEN 0x00000020
|
||||
#define SYS_UART_BIT_RX_INTEN 0x00000040
|
||||
#define SYS_UART_BIT_TX_IRQ 0x00000100
|
||||
#define SYS_UART_BIT_RX_IRQ 0x00000200
|
||||
#define SYS_UART_DATA SYS_UART0_DATA
|
||||
#define SYS_UART_STAT SYS_UART0_STAT
|
||||
#define SYS_UART_BAUD SYS_UART0_BAUD
|
||||
#define SYS_UART0_DATA (SYS_IO_BASE + 0x10000)
|
||||
#define SYS_UART0_STAT (SYS_IO_BASE + 0x10004)
|
||||
#define SYS_UART0_BAUD (SYS_IO_BASE + 0x10008)
|
||||
#define SYS_UART1_DATA (SYS_IO_BASE + 0x10100)
|
||||
#define SYS_UART1_STAT (SYS_IO_BASE + 0x10104)
|
||||
#define SYS_UART1_BAUD (SYS_IO_BASE + 0x10108)
|
||||
|
||||
// PS2s
|
||||
#define SYS_PS2_BIT_TX_EMPTY 0x00000001
|
||||
#define SYS_PS2_BIT_RX_AVAIL 0x00000004
|
||||
#define SYS_PS2_BIT_PIN_CLOCK 0x00000008
|
||||
#define SYS_PS2_BIT_PIN_DATA 0x00000010
|
||||
#define SYS_PS2_BIT_TX_INTEN 0x00000020
|
||||
#define SYS_PS2_BIT_RX_INTEN 0x00000040
|
||||
#define SYS_PS2_BIT_TX_IRQ 0x00000100
|
||||
#define SYS_PS2_BIT_RX_IRQ 0x00000200
|
||||
#define SYS_PS2_BIT_RX_ERR_PAR 0x00000800
|
||||
#define SYS_PS2_BIT_RX_ERR_FLAG 0x00008000
|
||||
#define SYS_PS2_0_DATA (SYS_IO_BASE + 0x10200)
|
||||
#define SYS_PS2_0_STAT (SYS_IO_BASE + 0x10204)
|
||||
#define SYS_PS2_1_DATA (SYS_IO_BASE + 0x10300)
|
||||
#define SYS_PS2_1_STAT (SYS_IO_BASE + 0x10304)
|
||||
|
||||
// USB
|
||||
#define SYS_USB_DATA (SYS_IO_BASE + 0x20000)
|
||||
#define SYS_USB_MBX (SYS_IO_BASE + 0x20004)
|
||||
#define SYS_USB_ADDR (SYS_IO_BASE + 0x20008)
|
||||
#define SYS_USB_STATUS (SYS_IO_BASE + 0x2000C)
|
||||
|
||||
// VGA
|
||||
#define SYS_VGA_CTRL (SYS_IO_BASE + 0x30000) // R/W
|
||||
#define SYS_VGA_BIT_CGRDY 0x00000001 // RO
|
||||
#define SYS_VGA_BIT_MSTEN 0x00000002 // R/W
|
||||
#define SYS_VGA_BIT_BUFCHG_INTEN 0x00000004 // RO
|
||||
#define SYS_VGA_BIT_BUFCHG_FLAG 0x00000008 // RO
|
||||
#define SYS_VGA_BIT_CLRSCR 0x00000010 // WO
|
||||
#define SYS_VGA_BIT_CLRLINE 0x00000020 // WO
|
||||
#define SYS_VGA_BIT_BLIT_REQ 0x00000100 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_BSY 0x00000100 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_FIN 0x00000200 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_FIN_ACK 0x00000200 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_FIN_INTEN 0x00000400 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_EMPTY 0x00000800 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_EMPTY_ACK 0x00000800 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_EMPTY_INTEN 0x00001000 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_OP_CONSTCOL 0x00010000 // R/W
|
||||
#define SYS_VGA_BIT_BLIT_ACTIVE 0x80000000 // RO
|
||||
#define SYS_VGA_ASCII (SYS_IO_BASE + 0x30004) // R/W
|
||||
#define SYS_VGA_POSX (SYS_IO_BASE + 0x30008) // R/W
|
||||
#define SYS_VGA_POSY (SYS_IO_BASE + 0x3000C) // R/W
|
||||
#define SYS_VGA_CGCOL (SYS_IO_BASE + 0x30010) // R/W
|
||||
#define SYS_VGA_RES (SYS_IO_BASE + 0x30014) // RO
|
||||
#define SYS_VGA_FB_FRONT (SYS_IO_BASE + 0x30018) // R/W
|
||||
#define SYS_VGA_FB_BACK (SYS_IO_BASE + 0x3001C) // R/W
|
||||
|
||||
#define SYS_VGA_BLIT_SRC0_ADDR (SYS_IO_BASE + 0x30020) // R/W
|
||||
#define SYS_VGA_BLIT_SRC0_DIMX (SYS_IO_BASE + 0x30024) // R/W
|
||||
#define SYS_VGA_BLIT_SRC1_ADDR (SYS_IO_BASE + 0x30030) // R/W
|
||||
#define SYS_VGA_BLIT_SRC1_DIMX (SYS_IO_BASE + 0x30034) // R/W
|
||||
#define SYS_VGA_BLIT_DST_ADDR (SYS_IO_BASE + 0x30040) // R/W
|
||||
#define SYS_VGA_BLIT_DST_DIMX (SYS_IO_BASE + 0x30044) // R/W
|
||||
#define SYS_VGA_BLIT_NX (SYS_IO_BASE + 0x30050) // R/W
|
||||
#define SYS_VGA_BLIT_NY (SYS_IO_BASE + 0x30054) // R/W
|
||||
#define SYS_VGA_BLIT_COLOR (SYS_IO_BASE + 0x30058) // R/W
|
||||
|
||||
// AC'97
|
||||
#define SYS_AC97_STAT (SYS_IO_BASE + 0x40000)
|
||||
#define SYS_AC97_CTRL (SYS_IO_BASE + 0x40000)
|
||||
#define SYS_AC97_ACSTAT (SYS_IO_BASE + 0x40400)
|
||||
#define SYS_AC97_ACCTRL (SYS_IO_BASE + 0x40600)
|
||||
#define SYS_AC97_PCM (SYS_IO_BASE + 0x40800)
|
||||
#define SYS_AC97_WAVIN SYS_AC97_PCM
|
||||
#define SYS_AC97_WAVOUT SYS_AC97_PCM
|
||||
|
||||
// Ethernet MAC
|
||||
#define SYS_EMAC_RX_CTRL (SYS_IO_BASE + 0x50000)
|
||||
#define EMAC_RX_CTRL_RESET (1 << 31)
|
||||
#define EMAC_RX_CTRL_GIGABIT (1 << 30)
|
||||
#define EMAC_RX_CTRL_FCS_CHECK (1 << 29)
|
||||
#define EMAC_RX_CTRL_PROMISCIOUS (1 << 23)
|
||||
#define EMAC_RX_CTRL_PKT_REQ (1 << 17)
|
||||
#define EMAC_RX_CTRL_PKT_FREE (1 << 16)
|
||||
#define EMAC_RX_CTRL_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_RX_STAT SYS_EMAC_RX_CTRL
|
||||
#define EMAC_RX_STAT_RESET (1 << 31)
|
||||
#define EMAC_RX_STAT_GIGABIT (1 << 30)
|
||||
#define EMAC_RX_STAT_FCS_CHECK (1 << 29)
|
||||
#define EMAC_RX_STAT_PROMISCIOUS (1 << 23)
|
||||
#define EMAC_RX_STAT_PKT_BCAST (1 << 19)
|
||||
#define EMAC_RX_STAT_PKT_MACOK (1 << 18)
|
||||
#define EMAC_RX_STAT_PKT_VALID (1 << 17)
|
||||
#define EMAC_RX_STAT_PKT_AVAIL (1 << 16)
|
||||
#define EMAC_RX_STAT_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_RX_SIZE (SYS_IO_BASE + 0x50004)
|
||||
|
||||
#define SYS_EMAC_TX_CTRL (SYS_IO_BASE + 0x50008)
|
||||
#define EMAC_TX_CTRL_RESET (1 << 31)
|
||||
#define EMAC_TX_CTRL_GIGABIT (1 << 30)
|
||||
#define EMAC_TX_CTRL_FCS_APPEND (1 << 29)
|
||||
#define EMAC_TX_CTRL_PKT_ALLOC (1 << 17)
|
||||
#define EMAC_TX_CTRL_PKT_COMMIT (1 << 16)
|
||||
#define EMAC_TX_CTRL_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_TX_STAT SYS_EMAC_TX_CTRL
|
||||
#define EMAC_TX_STAT_RESET (1 << 31)
|
||||
#define EMAC_TX_STAT_GIGABIT (1 << 30)
|
||||
#define EMAC_TX_STAT_FCS_APPEND (1 << 29)
|
||||
#define EMAC_TX_STAT_PKT_DONE (1 << 24)
|
||||
#define EMAC_TX_STAT_PKT_ALLOC_BSY (1 << 17)
|
||||
#define EMAC_TX_STAT_PKT_ARMED (1 << 16)
|
||||
#define EMAC_TX_STAT_INTEN (1 << 4)
|
||||
|
||||
#define SYS_EMAC_TX_SIZE (SYS_IO_BASE + 0x5000C)
|
||||
#define SYS_EMAC_MADDR (SYS_IO_BASE + 0x50018)
|
||||
#define SYS_EMAC_MADDR_0 SYS_EMAC_MADDR_0
|
||||
#define SYS_EMAC_MADDR_1 (SYS_IO_BASE + 0x5001C)
|
||||
|
||||
#define SYS_EMAC_DATA (SYS_IO_BASE + 0x58000)
|
||||
#define SYS_EMAC_RX_DATA SYS_EMAC_DATA
|
||||
#define SYS_EMAC_TX_DATA SYS_EMAC_DATA
|
||||
#define SYS_EMAC_DATA_CACHED (SYS_IO_BASE + 0x10008000)
|
||||
|
||||
// Sync. SRAM
|
||||
#define SYS_SSRAM_IO 0xA8000000
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// Chip registers
|
||||
// ---------------------------------------------------------
|
||||
@@ -306,17 +83,9 @@ void ICACHE_invalidate_at(uint32_t* pPtr);
|
||||
void DCACHE_invalidate_all(void);
|
||||
void DCACHE_invalidate_at(uint32_t* pPtr);
|
||||
|
||||
#define CALC_BAUD(b) \
|
||||
((uint32_t)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1);
|
||||
|
||||
#define UART0_setbaud(b) \
|
||||
*((uint32_t*)SYS_UART0_BAUD) = CALC_BAUD(b);
|
||||
|
||||
#define UART1_setbaud(b) \
|
||||
*((uint32_t*)SYS_UART1_BAUD) = CALC_BAUD(b);
|
||||
|
||||
#define UART2_setbaud(b) \
|
||||
*((uint32_t*)SYS_UART2_BAUD) = CALC_BAUD(b);
|
||||
void UART0_setbaud(uint32_t baudrate);
|
||||
void UART1_setbaud(uint32_t baudrate);
|
||||
void UART2_setbaud(uint32_t baudrate);
|
||||
|
||||
char readchar(uint32_t port);
|
||||
void writechar(uint32_t port, char c);
|
||||
|
||||
Reference in New Issue
Block a user