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- added SPI

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git-svn-id: http://moon:8086/svn/mips@45 a8ebac50-d88d-4704-bea3-6648445a41b3
This commit is contained in:
jens
2015-06-04 16:59:16 +00:00
parent 1357fd045a
commit 471a1dba4b
2 changed files with 53 additions and 7 deletions
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src/bootloader/libsys_boot.h
+27 -4
View File
@@ -57,10 +57,33 @@
#define SYS_UART_DATA (SYS_IO_BASE + 0x10000) #define SYS_UART_DATA (SYS_IO_BASE + 0x10000)
#define SYS_UART_STAT (SYS_IO_BASE + 0x10004) #define SYS_UART_STAT (SYS_IO_BASE + 0x10004)
#define SYS_UART_BAUD (SYS_IO_BASE + 0x10008) #define SYS_UART_BAUD (SYS_IO_BASE + 0x10008)
#define SYS_USB_DATA (SYS_IO_BASE + 0x20000)
#define SYS_USB_MBX (SYS_IO_BASE + 0x20004) #define SYS_SPI_CTRL_STAT (SYS_IO_BASE + 0x20000)
#define SYS_USB_ADDR (SYS_IO_BASE + 0x20008) // Read
#define SYS_USB_STATUS (SYS_IO_BASE + 0x2000C) #define SPI_CMD_STAT_CMDRDY (0x01)
#define SPI_CMD_STAT_DINRDY (0x02)
#define SPI_CMD_STAT_DOUTRDY (0x04)
#define SPI_CMD_STAT_CMD_FIFO_FULL (0x0100)
#define SPI_CMD_STAT_CMD_FIFO_EMPTY (0x0200)
#define SPI_CMD_STAT_WRITE_FIFO_FULL (0x0400)
#define SPI_CMD_STAT_WRITE_FIFO_EMPTY (0x0800)
#define SPI_CMD_STAT_READ_FIFO_FULL (0x1000)
#define SPI_CMD_STAT_READ_FIFO_EMPTY (0x2000)
#define SPI_CMD_STAT_RX_VALID (0x4000)
#define SPI_CMD_STAT_SPI_HOLD (0x8000)
// Write
#define SPI_CMD_CTRL_COMMIT (1)
#define SYS_SPI_XFER_SIZE (SYS_IO_BASE + 0x20004)
#define SYS_SPI_DATA_SIZE (SYS_IO_BASE + 0x20008)
#define SYS_SPI_DATA (SYS_IO_BASE + 0x2000C)
#define SYS_SPI_CTRL (SYS_IO_BASE + 0x20010)
#define SYS_UART_STAT (SYS_IO_BASE + 0x10004)
#define SYS_UART_BAUD (SYS_IO_BASE + 0x10008)
#define SYS_FLASH_IO 0xA4000000 #define SYS_FLASH_IO 0xA4000000
#define SYS_FLASH_MEM 0x00000000 #define SYS_FLASH_MEM 0x00000000
src/bootloader/test.c
+24 -1
View File
@@ -46,7 +46,11 @@ void main()
volatile uint32_t *pTim_stat = (uint32_t*)SYS_ITIM_STAT; volatile uint32_t *pTim_stat = (uint32_t*)SYS_ITIM_STAT;
volatile uint32_t *pTim0_cnt = (uint32_t*)SYS_ITIM0_CNT; volatile uint32_t *pTim0_cnt = (uint32_t*)SYS_ITIM0_CNT;
volatile uint32_t *pTim0_cmp = (uint32_t*)SYS_ITIM0_CMP; volatile uint32_t *pTim0_cmp = (uint32_t*)SYS_ITIM0_CMP;
volatile uint32_t *pSpiCtrlStat = (uint32_t*)SYS_SPI_CTRL_STAT;
volatile uint32_t *pSpiData = (uint32_t*)SYS_SPI_DATA;
volatile uint32_t *pSpiXferSize = (uint32_t*)SYS_SPI_XFER_SIZE;
volatile uint32_t *pSpiDataSize = (uint32_t*)SYS_SPI_DATA_SIZE;
volatile uint32_t *pSpiCtrl = (uint32_t*)SYS_SPI_CTRL;
*pTim0_cnt = 0; *pTim0_cnt = 0;
*pTim0_cmp = 2500000; // 50 ms @ 50 Mhz *pTim0_cmp = 2500000; // 50 ms @ 50 Mhz
*pTim_stat = (1 << 0); *pTim_stat = (1 << 0);
@@ -77,10 +81,29 @@ void main()
*pUART0_stat |= (1 << 6); *pUART0_stat |= (1 << 6);
sputs("Hello, world!\n"); sputs("Hello, world!\n");
k = 0; k = 0;
while(1) while(1)
{ {
sputs("Iteration # ");print_word(k);sputs("\n"); sputs("Iteration # ");print_word(k);sputs("\n");
sputs("Test SPI\n");
*pSpiCtrl = (*pSpiCtrl & 0xFFFFFF00) | 50;
*pSpiData = 0x9F000000;
*pSpiDataSize = 8;
*pSpiXferSize = 8+24;
*pSpiCtrlStat = SPI_CMD_CTRL_COMMIT;
sputs("SYS_SPI_CTRL_STAT : ");print_word(*pSpiCtrlStat);sputs("\n");
sputs("SYS_SPI_XFER_SIZE : ");print_word(*pSpiXferSize);sputs("\n");
sputs("SYS_SPI_DATA_SIZE : ");print_word(*pSpiDataSize);sputs("\n");
sputs("SYS_SPI_CTRL : ");print_word(*pSpiCtrl);sputs("\n");
while(!(*pSpiCtrlStat & SPI_CMD_STAT_DOUTRDY))
{
}
print_word(*pSpiData);sputs("\n");
sputs("Testing SDRAM (pattern)\n"); sputs("Testing SDRAM (pattern)\n");
for (j=0; j < ARRAY_SIZE(test_pattern); j++) for (j=0; j < ARRAY_SIZE(test_pattern); j++)
{ {