jens
16b6516d55
git-svn-id: http://moon:8086/svn/projects/ltspice@388 fda53097-d464-4ada-af97-ba876c37ca34
6068 lines
130 KiB
Plaintext
6068 lines
130 KiB
Plaintext
* AD549 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: 5/30V, JFET, OP, Low Ib, Precision, 1X
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* Developed by:
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* Revision History: 08/10/2012 - Updated to new header style
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* 1.1 ADSJ-HH 02/11 Changed some comment lines; delete spurious character on E3 line
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* 1.0 ADSJ-HH 08/09
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* Copyright 2009, 2012 by Analog Devices, Inc.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes: CAUTION!! To aid in convergence, most SPICE simulators
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* add conductance.
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* This is GMIN, and the default value is usually 1E-12. To properly
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* simulate the low input bias current and low current noise, the
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* Spice simulator options have to be set to the following:
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* .OPTIONS GMIN=0.1f
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* .OPTIONS ABSTOL=0.001pA
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* In many simulations, .OPTIONS STEPGMIN may have to be used.
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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*This model simulates typical values at Vs=+/-15V and 25 C only.
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* GBW & PM, Ibias, en, in, Ccm, Cdm, Isc, IVR
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* Not simulated/implemented - performance over temp and supply voltage
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*
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* END Notes
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*
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* Node assignments
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* Non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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.SUBCKT AD549 1 2 99 50 30
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*#ASSOC Category="Op-amps" symbol=opamp
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*
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* INPUT STAGE
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*
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RD1 4 50 4.621E+04
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RD2 6 50 4.621E+04
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Cdiff 1 2 5.400E-13; for 1pF total diff.
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Cin1 1 50 0.830E-12
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Cin2 2 50 0.830E-12
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I1 99 8 1.300E-04
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IOS 1 2 10.00E-15
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EOS 7 1 POLY(3) (22, 98) (73, 98) (81, 0) 45E-6 1 1 1 1
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V1 9a 8 DC 4.1
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D1 9a 99 DX
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J6 6 2 8 JX; D G S
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J7 4 7 8 JX
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Cph 4 5z 0.400E-13
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Rph 6 5z 1.00E+03
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GB2 7 50 POLY(3) (4, 7) (8, 7) (50, 7) 1.0E-14 -1E-16 -1E-16 -2E-16
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*
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EREF 98 0 24 0 1
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*
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* SECOND STAGE & POLE
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*
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R5 9 98 8.615E+06
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C3 9 98 1.000E-08
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G1 (9 98) (4 6) 4.500E-03
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V103 132 98 12.3
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D103 9 132 DX
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V104 133 98 -12.5
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D104 133 9 DX
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*
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* VOLTAGE NOISE GENERATOR
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*
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VN1 41 0 DC 2
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DN1 41 81 DEN
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DN2 81 43 DEN
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VN2 0 43 DC 2
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*
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* COMMON-MODE GAIN NETWORK WITH ZERO
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*
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R10 72 73 4.421E+03
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R20 73 98 1.592E-02
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C10 72 73 1.000E-06
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E3 72 98 POLY(2) (1, 98) (2, 98) 3.449E-00 3.449E-00
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*
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* PSRR WITH ZERO
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*
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EPSY 21 98 POLY(1) (50,99) -13.07E+00 1.332694E-01
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RPS1 21 22 5.134E+03
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RPS2 22 98 1.061E-01
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CPS1 21 22 1.000E-06
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*
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* POLE
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*
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R13 18 98 1.000E+03
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C9 18 98 1.100E-12
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G5 98 18 (9 98) 1.000E-03
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*
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* OUTPUT STAGE
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*
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R14 24 99 500E3
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R15 24 50 500E3
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GSY 99 50 POLY(1) (99 50) 468.0E-6 -0.5E-06
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R5a 29 99 200
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R6a 29 50 200
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L1 29 30 1E-09; 30 is output
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G6 27 50 18 29 5.000E-03
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G7 28 50 29 18 5.000E-03
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G5a 29 99 99 18 5.000E-03
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G6a 50 29 18 50 5.000E-03
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*
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V4 25 29 1.244
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D5 18 25 DX
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V5 29 26 1.244
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D6 26 18 DX
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F1 29 0 V4 1.00
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F2 0 29 V5 1.00
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*
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D3 99 27 DX
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D4 99 28 DX
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D7 50 27 DY
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D8 50 28 DY
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*
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* MODELS USED
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*
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.MODEL JX PJF(BETA=3.00E-04 VTO=-1.000 IS=2E-15 RD=1
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+ RS=1 CGD=2E-13 CGS=2E-13)
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.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12)
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.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
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.MODEL DEN D(IS=1E-12 RS=134100, KF=2.423E-15 AF=1)
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.MODEL DIN D(IS=1E-12 RS=12, KF=0 AF=1)
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.ENDS AD549
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*$
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* AD712 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: 10/30V, BIP, OP, Fast, Precision, 2X
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* Developed by: JCB/JW/PMI
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* Revision History: 08/10/2012 - Updated to new header style
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* 2.0 (04/1992) - Convert model into ADSpice format
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* Add noise generators
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* Copyright 1990, 2012 by Analog Devices.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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*
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* END Notes
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*
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* Node assignments
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* non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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.SUBCKT AD712 1 2 99 50 30
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*#ASSOC Category="Op-amps" symbol=opamp
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*
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* INPUT STAGE
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*
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R3 5 50 6.631
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R4 6 50 6.631
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CIN 1 2 5.5E-12
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I1 99 4 100E-3
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IOS 1 2 2.5E-12
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EOS 60 1 POLY(1) 17 24 100E-6 1
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EN 7 60 42 0 1
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GN1 0 1 45 0 1E-6
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GN2 0 2 48 0 1E-6
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J1 5 2 4 JX
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J2 6 7 4 JX
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GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12
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GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12
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*
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EREF 98 0 24 0 1
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*
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* VOLTAGE NOISE GENERATOR
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*
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VN1 41 0 DC 2
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DN1 41 42 DEN
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DN2 42 43 DEN
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VN2 0 43 DC 2
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*
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* CURRENT NOISE GENERATOR
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*
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VN3 44 0 DC 2
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DN3 44 45 DIN
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DN4 45 46 DIN
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VN4 0 46 DC 2
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*
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* CURRENT NOISE GENERATOR
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*
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VN5 47 0 DC 2
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DN5 47 48 DIN
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DN6 48 49 DIN
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VN6 0 49 DC 2
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*
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* SECOND STAGE & POLE AT 12 HZ
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*
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R5 9 98 2.65E6
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C3 9 98 5.00E-9
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G1 98 9 5 6 1.51E-1
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V2 99 8 1.3
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V3 10 50 1.9
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D1 9 8 DX
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D2 10 9 DX
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*
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* COMMON-MODE GAIN NETWORK WITH ZERO AT 300 HZ
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*
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R11 16 17 1E6
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C8 16 17 5.318E-10
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R12 17 98 1
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E3 16 98 POLY(2) 1 98 2 98 0 9.975 9.975
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*
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* POLE AT 15 MHZ
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*
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R13 18 98 1E3
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C9 18 98 10.61E-12
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G5 98 18 9 24 1E-3
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*
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* OUTPUT STAGE
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*
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R14 24 99 500E3
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R15 24 50 500E3
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CF 24 0 1E-6
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ISY 99 50 -95E-3
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R16 29 99 110
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R17 29 50 110
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L1 29 30 1E-8
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G6 27 50 18 29 9.09E-3
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G7 28 50 29 18 9.09E-3
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G8 29 99 99 18 9.09E-3
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G9 50 29 18 50 9.09E-3
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V4 25 29 0.675
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V5 29 26 0.675
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D3 18 25 DX
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D4 26 18 DX
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D5 99 27 DX
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D6 99 28 DX
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D7 50 27 DY
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D8 50 28 DY
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F1 29 0 V4 1
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F2 0 29 V5 1
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*
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* MODELS USED
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*
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.MODEL JX PJF(BETA=1.14E-1 VTO=-2.000 IS=20E-12 RD=0
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+ RS=0 CGD=1E-12 CGS=1E-12)
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.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12)
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.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
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.MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1)
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.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1)
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.ENDS AD712
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* AD713 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: 10/30V, BIP, OP, Fast, Precision, 4X
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* Developed by: JLW / PMI
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* Revision History: 08/10/2012 - Updated to new header style
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* 2.0 (03/1991) - Corrected VOS to be 0.2mV
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* Copyright 1991, 2012 by Analog Devices.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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* This version of the AD713 model simulates the typical
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* parameters corresponding to those in the device data
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* sheet.
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*
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* END Notes
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*
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* Node assignments
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* connections: non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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.SUBCKT AD713 13 15 12 16 14
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*#ASSOC Category="Op-amps" symbol=opamp
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*
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VOS 15 8 DC 0.2E-3
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EC 9 0 (14,0) 1
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C1 6 7 .5E-12
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RP 16 12 12E3
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GB 11 0 (3,0) 1.67E3
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RD1 6 16 16E3
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RD2 7 16 16E3
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ISS 12 1 DC 100E-6
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CCI 3 11 150E-12
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GCM 0 3 (0,1) 1.76E-9
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GA 3 0 (7,6) 2.3E-3
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RE 1 0 2.5E6
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RGM 3 0 1.69E3
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VC 12 2 DC 2.8
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VE 10 16 DC 2.8
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RO1 11 14 25
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CE 1 0 2E-12
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RO2 0 11 30
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RS1 1 4 5.77E3
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RS2 1 5 5.77E3
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J1 6 13 4 FET
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J2 7 8 5 FET
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DC 14 2 DIODE
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DE 10 14 DIODE
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DP 16 12 DIODE
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D1 9 11 DIODE
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D2 11 9 DIODE
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IOS 15 13 5E-12
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.MODEL DIODE D()
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.MODEL FET PJF(VTO=-1 BETA=1E-3 IS=40E-12)
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.ENDS AD713
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* AD746 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: Dual 500 ns Settling, BiFET Op Amp
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* Developed by: JLW / PMI
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* Revision History: 08/10/2012 - Updated to new header style
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* 2.0 (03/1991) - Corrected VOS to be 0.25mV
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* Copyright 1991, 2012 by Analog Devices.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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* This version of the AD746 model simulates the typical
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* parameters corresponding to those in the device data
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* sheet.
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*
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* END Notes
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*
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* Node assignments
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* connections: non-inverting input
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* | inverting input
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* | | positive power supply
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* | | | negative power supply
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* | | | | output
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* | | | | |
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.subckt AD746 11 14 10 16 13
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*#ASSOC Category="Op-amps" symbol=opamp
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*
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VOS 14 7 DC 0.25E-3
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EC 8 0 (13,0) 1
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C1 5 6 0.33E-12
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GB 12 0 (15,0) 1.67E3
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RD1 5 16 16E3
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RD2 6 16 16E3
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ISS 10 1 DC 100E-6
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GCM 0 15 (0,1) 1.76E-9
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GA 15 0 (6,5) 1.75E-3
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RE 1 0 2.5E6
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RGM 15 0 1.76E3
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VC 10 2 DC 2.8
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VE 9 16 DC 2.8
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RO1 12 13 25
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CE 1 0 1E-12
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RO2 0 12 30
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RS1 1 3 5.77E3
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RS2 1 4 5.77E3
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CCI 15 12 40E-12
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RP 16 10 8.5E3
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J1 5 11 3 FET
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J2 6 7 4 FET
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DC 13 2 DIODE
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DE 9 13 DIODE
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DP 16 10 DIODE
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D1 8 12 DIODE
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D2 12 8 DIODE
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.MODEL DIODE D()
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.MODEL FET PJF(VTO=-1 BETA=1E-3 IS=110E-12)
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.ENDS AD746
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* AD795 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: 8/30V, JFET, OP, Low Pwr, Low Noise, 1X
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* Developed by: JOM / ADSC
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* Revision History: 08/10/2012 - Updated to new header style
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* 1.0 (11/1994)
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* Copyright 1990, 2012 by Analog Devices.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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*
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* END Notes
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*
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* Node assignments
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* non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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.SUBCKT AD795 1 2 99 50 30
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*#ASSOC Category="Op-amps" symbol=opamp
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*
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* INPUT STAGE & POLE AT 40 MHZ
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*
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R3 5 50 .719
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R4 6 50 .719
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CIN 1 2 2E-12
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C2 5 6 1.383E-9
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I1 99 4 100E-3
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IOS 1 2 0.1E-12
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EOS 65 1 POLY(1) 17 24 50E-6 1
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J1 5 2 4 JX
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J2 6 7 4 JX
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EN 7 65 43 0 1
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GN1 0 1 47 0 1E-6
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GN2 0 2 61 0 1E-6
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GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12
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GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12
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*
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EREF 98 0 24 0 1
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*
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* VOLTAGE NOISE GENERATOR
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*
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VN1 41 0 DC 2
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RS1 41 42 8E3
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RS2 42 43 1.2E9
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CS1 42 43 398E-11
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RS3 43 44 1.2E9
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CS2 43 44 398E-11
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RS4 44 45 8E3
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VN2 0 45 DC 2
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*
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* CURRENT NOISE GENERATOR
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*
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VN3 46 0 DC 2
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RN5 46 47 41.5
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RN6 47 48 41.5
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VN4 0 48 DC 2
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*
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* CURRENT NOISE GENERATOR
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*
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VN5 60 0 DC 2
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RN7 60 61 41.5
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RN8 61 62 41.5
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VN6 0 62 DC 2
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*
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* SECOND STAGE & POLE AT 2.213 HZ
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*
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R5 9 98 719203
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C3 9 98 1.00E-7
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G1 98 9 5 6 1.39
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V2 99 8 3.025
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V3 10 50 3.025
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D1 9 8 DX
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D2 10 9 DX
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*
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* NEGATIVE ZERO AT 15 MHZ
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*
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R6 11 12 1E6
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R7 12 98 1
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E2 11 98 9 24 1E6
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VX1 84 0
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EX1 83 0 11 12 1
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FX1 11 12 VX1 -1
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CX1 83 84 10.6E-15
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*
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* POLE AT 20 MHZ
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*
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R8 13 98 1E3
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C5 13 98 7.96E-12
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G2 98 13 12 24 1E-3
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*
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* POLE AT 20 MHZ
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*
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R9 14 98 1E3
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C6 14 98 7.96E-12
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G3 98 14 13 24 1E-3
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*
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|
* POLE AT 20 MHZ
|
|
*
|
|
R10 15 98 1E3
|
|
C7 15 98 7.96E-12
|
|
G4 98 15 14 24 1E-3
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 300 HZ
|
|
*
|
|
R11 16 17 1E6
|
|
C8 16 17 5.3E-10
|
|
R12 17 98 1
|
|
E3 16 98 POLY(2) 1 98 2 98 0 1.585 1.585
|
|
*
|
|
* POLE AT 20 MHZ
|
|
*
|
|
R13 18 98 1E3
|
|
C9 18 98 7.96E-12
|
|
G5 98 18 15 24 1E-3
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R14 24 99 2000E3
|
|
R15 24 50 2000E3
|
|
FSY 99 50 POLY(2) V7 V8 -98.7E-3 1 1
|
|
R16 29 99 360
|
|
R17 29 50 360
|
|
L1 29 30 1E-8
|
|
G8 29 99 99 18 2.78E-3
|
|
G9 50 29 18 50 2.78E-3
|
|
V4 25 29 2.0
|
|
V5 29 26 2.0
|
|
D3 18 25 DX
|
|
D4 26 18 DX
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
G6 98 70 29 18 2.78E-3
|
|
D5 70 71 DX
|
|
D6 72 70 DX
|
|
V7 71 98 DC 0
|
|
V8 98 72 DC 0
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX PJF(BETA=9.67 VTO=-2.000 IS=0.50E-12 RD=0.1
|
|
+ RS=0.1 CGD=1E-15 CGS=1E-15)
|
|
.MODEL DX D(IS=1E-15 RS=10 CJO=1E-15)
|
|
.ENDS AD795
|
|
|
|
|
|
* AD820 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 5/30V, JFET, OP, S SPLY, RRO, 1X
|
|
* Developed by: JCB / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (08/1991)
|
|
* Copyright 1993, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD820 1 2 99 50 25
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE & POLE AT 3 MHZ
|
|
*
|
|
R3 5 99 2456
|
|
R4 6 99 2456
|
|
CIN 1 2 5E-12
|
|
C2 5 6 10.8E-12
|
|
I1 4 50 108E-6
|
|
IOS 1 2 1E-12
|
|
EOS 7 1 POLY(1) (12,98) 100E-6 1
|
|
J1 4 2 5 JX
|
|
J2 4 7 6 JX
|
|
*
|
|
EREF 98 0 30 0 1
|
|
*
|
|
* GAIN STAGE & POLE AT 124 HZ
|
|
*
|
|
R5 9 98 2.46E6
|
|
C3 9 25 35E-12
|
|
G1 98 9 6 5 4.07E-4
|
|
V1 8 98 0
|
|
V2 98 10 -1
|
|
D1 9 10 DX
|
|
D2 8 9 DX
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 KHZ
|
|
*
|
|
R21 11 12 1E6
|
|
R22 12 98 1
|
|
C14 11 12 159E-12
|
|
E13 11 98 POLY(2) (2,98) (1,98) 0 50 50
|
|
*
|
|
* POLE AT 10 MHZ
|
|
*
|
|
R23 18 98 1E6
|
|
C15 18 98 15.9E-15
|
|
G15 98 18 9 98 1E-6
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
ES 26 51 POLY(1) (18,98) 1.72 1
|
|
RS 26 22 500
|
|
V3 23 51 1.1
|
|
V4 21 23 1.36
|
|
C16 20 25 2E-12
|
|
C17 24 25 2E-12
|
|
RG1 20 97 1E8
|
|
RG2 24 97 1E8
|
|
Q1 20 20 97 PNP
|
|
Q2 20 21 22 NPN
|
|
Q3 24 23 22 PNP
|
|
Q4 24 24 51 NPN
|
|
Q5 25 20 97 PNP 20
|
|
Q6 25 24 51 NPN 20
|
|
VP 96 97 0
|
|
VN 51 52 0
|
|
EP 96 0 POLY(1) (99,0) 0.01 1
|
|
EN 52 0 POLY(1) (50,0) -0.015 1
|
|
*
|
|
R25 30 99 5E6
|
|
R26 30 50 5E6
|
|
FSY1 99 0 VP 1
|
|
FSY2 0 50 VN 1
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=1E-12)
|
|
.MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
|
|
+ RE=4 RC=200 IS=1E-16)
|
|
.MODEL PNP PNP(BF=80 VAF=150 VAR=15 RB=2E3
|
|
+ RE=4 RC=900 IS=1E-16)
|
|
.MODEL DX D(IS=1E-15)
|
|
.ENDS AD820
|
|
|
|
|
|
|
|
|
|
|
|
* AD822 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: J5/30V, JFET, OP, S SPLY, RRO, 2X
|
|
* Developed by: ARG / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (02/1995)
|
|
* Copyright 1995, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD822 1 2 99 50 25
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE & POLE AT 5 MHZ
|
|
*
|
|
R3 5 99 2456
|
|
R4 6 99 2456
|
|
CIN 1 2 5E-12
|
|
C2 5 6 6.48E-12
|
|
I1 4 50 108E-6
|
|
IOS 1 2 1E-12
|
|
EOS 7 1 POLY(1) (12,98) 100E-6 1
|
|
J1 5 2 4 JX
|
|
J2 6 7 4 JX
|
|
GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12
|
|
GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12
|
|
*
|
|
* GAIN STAGE & POLE AT 13.4 HZ
|
|
*
|
|
EREF 98 0 (30,0) 1
|
|
R5 9 98 2.313E6
|
|
C3 9 25 32E-12
|
|
G1 98 9 (6,5) 4.07E-4
|
|
V1 8 98 0
|
|
V2 98 10 -1
|
|
D1 9 10 DX
|
|
D2 8 9 DX
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 KHZ
|
|
*
|
|
R21 11 12 1E6
|
|
R22 12 98 100
|
|
C14 11 12 159E-12
|
|
E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5
|
|
*
|
|
* POLE AT 10 MHZ
|
|
*
|
|
R23 18 98 1E6
|
|
C15 18 98 15.9E-15
|
|
G15 98 18 (9,98) 1E-6
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
ES 26 51 POLY(1) (18,98) 1.72 1
|
|
RS 26 22 500
|
|
V3 23 51 1.03951
|
|
V4 21 23 1.36
|
|
C16 20 25 2E-12
|
|
C17 24 25 2E-12
|
|
RG1 20 97 1E8
|
|
RG2 24 97 1E8
|
|
Q1 20 20 97 PNP
|
|
Q2 20 21 22 NPN
|
|
Q3 24 23 22 PNP
|
|
Q4 24 24 51 NPN
|
|
Q5 25 20 97 PNP 20
|
|
Q6 25 24 51 NPN 20
|
|
VP 96 97 0
|
|
VN 51 52 0
|
|
EP 96 0 POLY(1) (99,0) 0.01 1
|
|
EN 52 0 POLY(1) (50,0) -0.015 1
|
|
R25 30 99 63.5E3
|
|
R26 30 50 63.5E3
|
|
FSY1 99 0 VP 1
|
|
FSY2 0 50 VN 1
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=1E-12)
|
|
.MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200)
|
|
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900)
|
|
.MODEL DX D(IS=1E-15)
|
|
.ENDS AD822
|
|
|
|
|
|
|
|
|
|
|
|
* AD823 Spice Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: Dual 16MHz FET amplifier
|
|
* Developed by: SMR
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 4.0 (04/1997)
|
|
* Copyright 1996, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.
|
|
* Use of this model indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
* Distortion is not characterized
|
|
*
|
|
* Parameters modeled include:
|
|
* open loop gain and phase vs frequency
|
|
* output clamping voltage and current input common mode range
|
|
* CMRR vs freq
|
|
* I bias vs Vcm in
|
|
* Slew rate
|
|
* Output currents are reflected to V supplies
|
|
* Voltage and current noise density are accurate for the entire bandwidth of the AD823
|
|
* Vos is static and will not vary with Vcm input
|
|
* Step response is modeled at unity gain w/1k load
|
|
* This model of the AD823 works at 3.3v
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD823 1 2 99 50 11
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
|
|
***** Input Stage/pole at 50mhz
|
|
|
|
R1 1 13 5e12
|
|
R2 13 2 5e12
|
|
fn1 98 1 vn2 1
|
|
fn2 98 2 vn2 1
|
|
cin1 1 98 1.8e-12
|
|
cin2 2 98 1.8e-12
|
|
J1 24 1 25 jx
|
|
J2 24 14 26 jx
|
|
R3 99 25 708
|
|
R4 99 26 708
|
|
Cp 25 26 0.65pf
|
|
Ibt 24 50 0.62ma
|
|
Ib1 1 98 5p
|
|
Ib2 2 98 5p
|
|
Eos 2 12 poly(1) 34 98 0.2e-3 1
|
|
Enoise 12 14 36 98 1
|
|
|
|
***** Input V noise source
|
|
|
|
dn1 35 98 dn1
|
|
rn1 35 98 6.5e-5
|
|
vn1 35 98 0
|
|
|
|
hn1 36 98 vn1 1
|
|
rn2 36 98 1
|
|
|
|
***** Input I noise source
|
|
|
|
rn3 37 98 1.6e10
|
|
vn2 37 98 0
|
|
|
|
hn2 38 98 vn2 1
|
|
rn4 38 98 1
|
|
|
|
***** Gain Stage & Pole @ 300Hz
|
|
|
|
*Vd1 99 3 0.91
|
|
*Vd2 4 50 0.91
|
|
Vd1 99 3 0.61
|
|
Vd2 4 50 0.64
|
|
Gg1 99 5 (26,25) 1.413e-3
|
|
Gg2 5 50 (25,26) 1.413e-3
|
|
D1 5 3 dx
|
|
D2 4 5 dx
|
|
Rg1 99 5 21.23e6
|
|
Rg2 50 5 21.23e6
|
|
Cdp1 99 5 25pf
|
|
Cdp2 50 5 25pf
|
|
|
|
***** Internal Reference
|
|
|
|
Eref1 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5
|
|
Eref2 97 0 poly(2) (1,0) (2,0) 0 0.5 0.5
|
|
|
|
***** Common Mode Gain Network/Pole at 10khz
|
|
|
|
Gacm1 15 98 98 97 1.4
|
|
Lacm2 15 29 10e-9
|
|
Racm2 29 98 1e-3
|
|
|
|
***** Common Mode Gain Network/Zero at 300hz
|
|
|
|
Ecm1 30 98 15 98 70e-3
|
|
Racm3 30 31 1.67e3
|
|
Racm4 31 32 100e-3
|
|
Lacm3 32 98 53e-6
|
|
|
|
***** Common Mode Gain Network/Pole at 5mhz
|
|
|
|
Ecm2 33 98 31 98 1
|
|
Lacm4 33 34 31.8u
|
|
Racm 34 98 1k
|
|
|
|
***** Zero/Pole Stages (20MHz/50MHz))
|
|
|
|
ezp 16 98 5 98 2.5
|
|
rzp1 16 17 188
|
|
rzp2 17 18 126
|
|
lzp 18 98 1u
|
|
|
|
***** Buffer to output stage
|
|
|
|
gbuf 98 19 17 98 1e-4
|
|
Rbuf 19 98 10k
|
|
|
|
***** Output Stage
|
|
|
|
fo1 98 90 vcd 1
|
|
Do1 90 91 dx
|
|
Do2 92 90 dx
|
|
vi1 91 98 0
|
|
vi2 98 92 0
|
|
|
|
*fsy 99 50 poly(2) vi1 vi2 5.7e-3 1 1
|
|
Isy 99 50 5.7e-3
|
|
Eref 96 0 11 0 1
|
|
fsy1 99 96 poly(2) vi1 vcd 0 1 -.5
|
|
fsy2 96 50 poly(2) vi2 vcd 0 1 0.5
|
|
|
|
|
|
|
|
Go3 10 99 99 19 50m
|
|
Go4 50 10 19 50 50m
|
|
Ro3 99 10 20
|
|
Ro4 10 50 20
|
|
vcd 10 95 0
|
|
lo1 95 11 1e-10
|
|
ro 11 98 1e6
|
|
Do5 19 20 dx
|
|
Do6 21 19 dx
|
|
Vo1 20 10 -0.3
|
|
Vo2 10 21 -0.4
|
|
|
|
.model dx d(IS=1e-15)
|
|
.model dn1 d(is=1e-15 af=0 kf=1e-12)
|
|
.model jx njf(beta=3e-3 vto=-1 Is=1e-12)
|
|
.ends AD823
|
|
|
|
|
|
|
|
|
|
|
|
* AD823A Spice Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc:
|
|
* Developed by: SMR
|
|
* Revision History:
|
|
* 1.0 (4/2012) Updated to new header style
|
|
* Copyright 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to
|
|
* http://www.analog.com/Analog_Root/static/techSupport/designTools/
|
|
* spiceModels/license/spice_general.html for License Statement.
|
|
* Use of this model indicates your acceptance with the terms and
|
|
* provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
* Distortion
|
|
*
|
|
*
|
|
* Parameters modeled include:
|
|
* open loop gain and phase vs frequency
|
|
* output clamping voltage and current
|
|
* input common mode range
|
|
* CMRR vs freq
|
|
* I bias vs Vcm in
|
|
* Slew rate
|
|
* Output currents are reflected to V supplies
|
|
* Voltage and current noise density are accurate for the entire bandwidth of the AD823A
|
|
* Vos is static and will not vary with Vcm input
|
|
* Step response is modeled at unity gain w/1k load
|
|
* This model of the AD823A works at 3.3v
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD823A 1 2 99 50 11
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
|
|
***** Input Stage/pole at 50mhz
|
|
|
|
R1 1 13 5e12
|
|
R2 13 2 5e12
|
|
fn1 98 1 vn2 1
|
|
fn2 98 2 vn2 1
|
|
cin1 1 98 1.8e-12
|
|
cin2 2 98 1.8e-12
|
|
J1 24 1 25 jx
|
|
J2 24 14 26 jx
|
|
R3 99 25 708
|
|
R4 99 26 708
|
|
Cp 25 26 0.65pf
|
|
Ibt 24 50 0.62ma
|
|
Ib1 1 98 5p
|
|
Ib2 2 98 5p
|
|
Eos 2 12 poly(1) 34 98 0.2e-3 1
|
|
Enoise 12 14 36 98 1
|
|
|
|
***** Input V noise source
|
|
|
|
dn1 35 98 dn1
|
|
rn1 35 98 6.5e-5
|
|
vn1 35 98 0
|
|
|
|
hn1 36 98 vn1 1
|
|
rn2 36 98 1
|
|
|
|
***** Input I noise source
|
|
|
|
rn3 37 98 1.6e10
|
|
vn2 37 98 0
|
|
|
|
hn2 38 98 vn2 1
|
|
rn4 38 98 1
|
|
|
|
***** Gain Stage & Pole @ 300Hz
|
|
|
|
*Vd1 99 3 0.91
|
|
*Vd2 4 50 0.91
|
|
Vd1 99 3 0.61
|
|
Vd2 4 50 0.64
|
|
Gg1 99 5 (26,25) 1.413e-3
|
|
Gg2 5 50 (25,26) 1.413e-3
|
|
D1 5 3 dx
|
|
D2 4 5 dx
|
|
Rg1 99 5 21.23e6
|
|
Rg2 50 5 21.23e6
|
|
Cdp1 99 5 25pf
|
|
Cdp2 50 5 25pf
|
|
|
|
***** Internal Reference
|
|
|
|
Eref1 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5
|
|
Eref2 97 0 poly(2) (1,0) (2,0) 0 0.5 0.5
|
|
|
|
***** Common Mode Gain Network/Pole at 10khz
|
|
|
|
Gacm1 15 98 98 97 1.4
|
|
Lacm2 15 29 10e-9
|
|
Racm2 29 98 1e-3
|
|
|
|
***** Common Mode Gain Network/Zero at 300hz
|
|
|
|
Ecm1 30 98 15 98 70e-3
|
|
Racm3 30 31 1.67e3
|
|
Racm4 31 32 100e-3
|
|
Lacm3 32 98 53e-6
|
|
|
|
***** Common Mode Gain Network/Pole at 5mhz
|
|
|
|
Ecm2 33 98 31 98 1
|
|
Lacm4 33 34 31.8u
|
|
Racm 34 98 1k
|
|
|
|
***** Zero/Pole Stages (20MHz/50MHz))
|
|
|
|
ezp 16 98 5 98 2.5
|
|
rzp1 16 17 188
|
|
rzp2 17 18 126
|
|
lzp 18 98 1u
|
|
|
|
***** Buffer to output stage
|
|
|
|
gbuf 98 19 17 98 1e-4
|
|
Rbuf 19 98 10k
|
|
|
|
***** Output Stage
|
|
|
|
fo1 98 90 vcd 1
|
|
Do1 90 91 dx
|
|
Do2 92 90 dx
|
|
vi1 91 98 0
|
|
vi2 98 92 0
|
|
|
|
*fsy 99 50 poly(2) vi1 vi2 5.7e-3 1 1
|
|
Isy 99 50 5.7e-3
|
|
Eref 96 0 11 0 1
|
|
fsy1 99 96 poly(2) vi1 vcd 0 1 -.5
|
|
fsy2 96 50 poly(2) vi2 vcd 0 1 0.5
|
|
|
|
|
|
|
|
Go3 10 99 99 19 50m
|
|
Go4 50 10 19 50 50m
|
|
Ro3 99 10 20
|
|
Ro4 10 50 20
|
|
vcd 10 95 0
|
|
lo1 95 11 1e-10
|
|
ro 11 98 1e6
|
|
Do5 19 20 dx
|
|
Do6 21 19 dx
|
|
Vo1 20 10 -0.3
|
|
Vo2 10 21 -0.4
|
|
|
|
.model dx d(IS=1e-15)
|
|
.model dn1 d(is=1e-15 af=0 kf=1e-12)
|
|
.model jx njf(beta=3e-3 vto=-1 Is=1e-12)
|
|
.ends AD823A
|
|
* AD824 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 5/30V, JFET, OP, S SPLY, RRO, 4X
|
|
* Developed by: ARG / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (09/1994)
|
|
* Copyright 1993, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD824 1 2 99 50 25
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE & POLE AT 3.1MHZ
|
|
*
|
|
R3 5 99 1.193E3
|
|
R4 6 99 1.193E3
|
|
CIN 1 2 4E-12
|
|
C2 5 6 19.229E-12
|
|
I1 4 50 108E-6
|
|
IOS 1 2 1E-12
|
|
EOS 7 1 POLY(1) (12,98) 100E-6 1
|
|
J1 4 2 5 JX
|
|
J2 4 7 6 JX
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE
|
|
*
|
|
EREF 98 0 (30,0) 1
|
|
R5 9 98 2.205E6
|
|
C3 9 25 54E-12
|
|
G1 98 9 (6,5) 0.838E-3
|
|
V1 8 98 -1
|
|
V2 98 10 -1
|
|
D1 9 10 DX
|
|
D2 8 9 DX
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1KHZ
|
|
*
|
|
R21 11 12 1E6
|
|
R22 12 98 100
|
|
C14 11 12 159E-12
|
|
E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5
|
|
*
|
|
* POLE AT 10MHZ
|
|
*
|
|
R23 18 98 1E6
|
|
C15 18 98 15.9E-15
|
|
G15 98 18 (9,98) 1E-6
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
ES 26 98 (18,98) 1
|
|
RS 26 22 500
|
|
IB1 98 21 2.404E-3
|
|
IB2 23 98 2.404E-3
|
|
D10 21 98 DY
|
|
D11 98 23 DY
|
|
C16 20 25 2E-12
|
|
C17 24 25 2E-12
|
|
DQ1 97 20 DQ
|
|
Q2 20 21 22 NPN
|
|
Q3 24 23 22 PNP
|
|
DQ2 24 51 DQ
|
|
Q5 25 20 97 PNP 20
|
|
Q6 25 24 51 NPN 20
|
|
VP 96 97 0
|
|
VN 51 52 0
|
|
EP 96 0 (99,0) 1
|
|
EN 52 0 (50,0) 1
|
|
R25 30 99 5E6
|
|
R26 30 50 5E6
|
|
FSY1 99 0 VP 1
|
|
FSY2 0 50 VN 1
|
|
DC1 25 99 DX
|
|
DC2 50 25 DX
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12)
|
|
.MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
|
|
+ RE=4 RC=550 IS=1E-16)
|
|
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3
|
|
+ RE=4 RC=750 IS=1E-16)
|
|
.MODEL DX D(IS=1E-15)
|
|
.MODEL DY D()
|
|
.MODEL DQ D(IS=1E-16)
|
|
.ENDS AD824
|
|
|
|
|
|
|
|
|
|
|
|
*AD8682 Macro-model
|
|
*Function:Amplifier
|
|
*
|
|
*Revision History:
|
|
*Rev.1 Nov 2016-ZZ
|
|
*Copyright 2016 by Analog Devices
|
|
*
|
|
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
|
|
*for License Statement. Use of this model indicates your acceptance
|
|
*of the terms and provisions in the License Staement.
|
|
*
|
|
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
|
|
*
|
|
*Not modeled: Distortion, PSRR, Overload Recovery,
|
|
* Shutdown Turn On/Turn Off time
|
|
*
|
|
*Parameters modeled include:
|
|
* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
|
|
* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
|
|
* Capacitive load drive, Quiescent and dynamic supply currents,
|
|
* Shut Down pin functionality where applicable,
|
|
* Single supply & offset supply functionality.
|
|
*
|
|
*Node Assignments
|
|
* Non-Inverting Input
|
|
* | Inverting Input
|
|
* | | Positive supply
|
|
* | | | Negative supply
|
|
* | | | | Output
|
|
* | | | | |
|
|
.Subckt AD8682 100 101 102 103 104
|
|
*
|
|
***Power Supplies***
|
|
Rz1 102 1020 Rideal 1e-6
|
|
Rz2 103 1030 Rideal 1e-6
|
|
Ibias 1020 1030 dc 0.44e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 3.96e-3
|
|
S1 98 1030 106 113 Switch
|
|
R1 1020 99 Rideal 1e7
|
|
R2 99 1030 Rideal 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
S2 1 100 106 113 Switch
|
|
S3 9 101 106 113 Switch
|
|
VOS 1 2 dc 2.5e-3
|
|
IbiasP 110 2 dc 2e-12
|
|
IbiasN 110 9 dc 2e-12
|
|
RinCMP 110 2 Rideal 2000e6
|
|
RinCMN 9 110 Rideal 2000e6
|
|
CinCMP 110 2 2.2e-12
|
|
CinCMN 9 110 2.2e-12
|
|
IOS 9 2 1e-15
|
|
RinDiff 9 2 Rideal 10000e3
|
|
CinDiff 9 2 0.8e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 Rideal 1e3
|
|
RX1 40 3 Rideal 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 0.46
|
|
VinN 42 112 dc 4.46
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.7071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.7071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.7071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.7071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 Rideal 1e12
|
|
RcmrrN 10 9 Rideal 1e12
|
|
g10 11 110 10 110 -6.325e-9
|
|
Lcmrr 11 12 15.9e-3
|
|
Rcmrr 12 110 Rideal 1e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
***Power Down***
|
|
VPD 111 80 dc 2
|
|
VPD1 81 0 dc 1.5
|
|
RPD 111 106 Rideal 1e6
|
|
ePD 80 113 82 0 1
|
|
RDP1 82 0 Rideal 1e3
|
|
CPD 82 0 1e-10
|
|
S5 81 82 83 113 Switch
|
|
CDP1 83 0 1e-12
|
|
RPD2 106 83 1e6
|
|
*
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 104 Rideal 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 Rideal 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 0.08 Hz***
|
|
g210 210 110 200 110 0.0636e-6
|
|
R210 210 110 Rideal 1989.43e6
|
|
C210 210 110 1e-012
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 Rideal 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 6.095
|
|
VoutN 64 66 dc 6.095
|
|
e60 65 110 111 110 1
|
|
e61 66 110 112 110 1
|
|
*
|
|
*
|
|
***Pole at 12MHz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 Rideal 1000
|
|
C220 220 110 13.2629e-12
|
|
*
|
|
***Pole at 12MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 Rideal 1000
|
|
C230 230 110 13.2629e-12
|
|
*
|
|
***Pole at 12MHz***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 Rideal 1000
|
|
C240 240 110 13.2629e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 Rideal 1000
|
|
C245 245 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 Rideal 1000
|
|
C250 250 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 Rideal 1000
|
|
C255 255 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 Rideal 1000
|
|
C260 260 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 Rideal 1000
|
|
C265 265 110 3.1831e-12
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 Rideal 10
|
|
*
|
|
***Peak: f=50MHz, Zeta=0.7, Gain=0.2dB***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 Rideal 10
|
|
L290 290 291 22.736e-9
|
|
C290 291 292 445.633e-12
|
|
R291 292 110 Rideal 429.314
|
|
e295 295 110 292 110 1.0233
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 Rideal 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 Rideal .3
|
|
Lout 303 310 1e-9
|
|
Cout 310 110 1e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc -0.364
|
|
VIoutN 304 306 dc 0.136
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 Rideal 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 1.785
|
|
VoutN1 74 112 dc 1.785
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 Rideal 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 Rideal 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc 102 314 diode
|
|
RX5 311 312 Rideal 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 Rideal 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 103 diode
|
|
*
|
|
*
|
|
***Output Switch***
|
|
S4 104 313 106 113 Switch
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=142.026)
|
|
.model DzSlewN D(BV=142.026)
|
|
.model DVnoisy D(IS=4.90e-14 KF=3.04e-18)
|
|
.model DINnoisy D(IS=3.81e-21 KF=0.00e0)
|
|
.model DIPnoisy D(IS=3.81e-21 KF=0.00e0)
|
|
.model Rideal res(T_ABS=-273)
|
|
*
|
|
.ends
|
|
*AD8684 Macro-model
|
|
*Function:Amplifier
|
|
*
|
|
*Revision History:
|
|
*Rev.1 Nov 2016-ZZ
|
|
*Copyright 2016 by Analog Devices
|
|
*
|
|
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
|
|
*for License Statement. Use of this model indicates your acceptance
|
|
*of the terms and provisions in the License Staement.
|
|
*
|
|
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
|
|
*
|
|
*Not modeled: Distortion, PSRR, Overload Recovery,
|
|
* Shutdown Turn On/Turn Off time
|
|
*
|
|
*Parameters modeled include:
|
|
* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
|
|
* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
|
|
* Quiescent and dynamic supply currents,
|
|
* Single supply & offset supply functionality.
|
|
*
|
|
*Node Assignments
|
|
* Non-Inverting Input
|
|
* | Inverting Input
|
|
* | | Positive supply
|
|
* | | | Negative supply
|
|
* | | | | Output
|
|
* | | | | |
|
|
.Subckt AD8684 100 101 102 103 104
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
***Power Supplies***
|
|
Rz1 102 1020 Rideal 1e-6
|
|
Rz2 103 1030 Rideal 1e-6
|
|
Ibias 1020 1030 dc 0.44e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 3.96e-3
|
|
S1 98 1030 106 113 Switch
|
|
R1 1020 99 Rideal 1e7
|
|
R2 99 1030 Rideal 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
S2 1 100 106 113 Switch
|
|
S3 9 101 106 113 Switch
|
|
VOS 1 2 dc 3.5e-3
|
|
IbiasP 110 2 dc 5e-12
|
|
IbiasN 110 9 dc 5e-12
|
|
RinCMP 110 2 Rideal 2000e6
|
|
RinCMN 9 110 Rideal 2000e6
|
|
CinCMP 110 2 2.2e-12
|
|
CinCMN 9 110 2.2e-12
|
|
IOS 9 2 10e-15
|
|
RinDiff 9 2 Rideal 10000e3
|
|
CinDiff 9 2 0.8e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 Rideal 1e3
|
|
RX1 40 3 Rideal 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 0.46
|
|
VinN 42 112 dc 4.46
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.7071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.7071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.7071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.7071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 Rideal 1e12
|
|
RcmrrN 10 9 Rideal 1e12
|
|
g10 11 110 10 110 -6.325e-9
|
|
Lcmrr 11 12 22.59e-3
|
|
Rcmrr 12 110 Rideal 5e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
***Power Down***
|
|
VPD 111 80 dc 2
|
|
VPD1 81 0 dc 1.5
|
|
RPD 111 106 Rideal 1e6
|
|
ePD 80 113 82 0 1
|
|
RDP1 82 0 Rideal 1e3
|
|
CPD 82 0 1e-10
|
|
S5 81 82 83 113 Switch
|
|
CDP1 83 0 1e-12
|
|
RPD2 106 83 1e6
|
|
*
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 104 Rideal 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 Rideal 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 0.08 Hz***
|
|
g210 210 110 200 110 0.0636e-6
|
|
R210 210 110 Rideal 1989.43e6
|
|
C210 210 110 1e-012
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 Rideal 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 6.095
|
|
VoutN 64 66 dc 6.095
|
|
e60 65 110 111 110 1
|
|
e61 66 110 112 110 1
|
|
*
|
|
*
|
|
***Pole at 12MHz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 Rideal 1000
|
|
C220 220 110 13.2629e-12
|
|
*
|
|
***Pole at 12MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 Rideal 1000
|
|
C230 230 110 13.2629e-12
|
|
*
|
|
***Pole at 12MHz***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 Rideal 1000
|
|
C240 240 110 13.2629e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 Rideal 1000
|
|
C245 245 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 Rideal 1000
|
|
C250 250 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 Rideal 1000
|
|
C255 255 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 Rideal 1000
|
|
C260 260 110 3.1831e-12
|
|
*
|
|
***Pole at 50MHz***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 Rideal 1000
|
|
C265 265 110 3.1831e-12
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 Rideal 10
|
|
*
|
|
***Peak: f=50MHz, Zeta=0.7, Gain=0.2dB***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 Rideal 10
|
|
L290 290 291 22.736e-9
|
|
C290 291 292 445.633e-12
|
|
R291 292 110 Rideal 429.314
|
|
e295 295 110 292 110 1.0233
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 Rideal 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 Rideal .3
|
|
Lout 303 310 1e-9
|
|
Cout 310 110 1e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc -0.364
|
|
VIoutN 304 306 dc 0.136
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 Rideal 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 1.785
|
|
VoutN1 74 112 dc 1.785
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 Rideal 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 Rideal 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc 102 314 diode
|
|
RX5 311 312 Rideal 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 Rideal 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 103 diode
|
|
*
|
|
*
|
|
***Output Switch***
|
|
S4 104 313 106 113 Switch
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=142.026)
|
|
.model DzSlewN D(BV=142.026)
|
|
.model DVnoisy D(IS=4.90e-14 KF=3.04e-18)
|
|
.model DINnoisy D(IS=3.81e-21 KF=0.00e0)
|
|
.model DIPnoisy D(IS=3.81e-21 KF=0.00e0)
|
|
.model Rideal res(T_ABS=-273)
|
|
*
|
|
.ends AD8684* ADA4091 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 2X
|
|
* Developed by: HH / AD-SJ
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 05/14/2014 - ported to Simplis (JSW)
|
|
* 0.0 (04/2009)
|
|
* Copyright 2008, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT ADA4091 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
I1 99 7 8.00E-06
|
|
Q1 6 4 7A QP
|
|
Q2 5 3 7B QP
|
|
RE1 7A 7 7.774E+02
|
|
RE2 7B 7 7.774E+02
|
|
D1 3 99 DX
|
|
D2 4 99 DX
|
|
D3 50 3 DX
|
|
D4 50 4 DX
|
|
D5 3 4 DX
|
|
D6 4 3 DX
|
|
R1 3 8 5E+03
|
|
R2 4 2 5E+03
|
|
R3 5 50 7.500E4;
|
|
R4 6 50 7.500E4;
|
|
Cph 5 5A 0.235E-12
|
|
Rph 5A 6 300
|
|
EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -400E-9 1 1 1 1
|
|
IOS 3 4 -50E-12
|
|
CDiff 1 2 2.5E-12
|
|
Cin1 1 50 2E-12
|
|
Cin2 2 50 2E-12
|
|
*
|
|
* INPUT PROTECTION NETWORK
|
|
*
|
|
X_in1 1 50 Diac1
|
|
X_in2 2 50 Diac1
|
|
X_in3 1 99 Diac1
|
|
X_in4 2 99 Diac1
|
|
*
|
|
*
|
|
RS1 99 39 400.0E3
|
|
RS2 39 50 400.0E3
|
|
EREF 98 0 (39,0) 1
|
|
*
|
|
* 1ST GAIN STAGE
|
|
*
|
|
G1 9 98 (6,5) 1.0E-06
|
|
R7 9 98 1E6
|
|
*
|
|
* 2ND GAIN STAGE AND DOMINANT POLE
|
|
*
|
|
R8 12 98 1.094E+08
|
|
G2 12 98 (98,9) 3.881E-06
|
|
D7 12 13 DX
|
|
D8 14 12 DX
|
|
V1 13 98 +0.2; source
|
|
V2 14 98 -0.2; sink
|
|
*
|
|
* Provision for second pole
|
|
*
|
|
G3 18 98 (98,12) 1E-05
|
|
R11 18 98 1E5
|
|
*
|
|
* CMRR=90dB, Pole at 1100 Hz
|
|
*
|
|
ECM 21 98 POLY(2) (1,98) (2,98) 0 1.318E-01 1.318E-01
|
|
R10 21 22 1.326E+05
|
|
R20 22 98 1.592E+01
|
|
C10 21 22 1E-9
|
|
*
|
|
* PSRR=85dB, POLE AT 300 Hz
|
|
*
|
|
EPSY 72 98 POLY(1) (99,50) +0.1E-1 1.770E+01
|
|
RPS1 72 73 7.958E+02
|
|
RPS2 73 98 3.183E-03
|
|
CPS1 72 73 1.00E-06
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 24nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 96.300E-3
|
|
HN 81 98 VN1 2.397E+01
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER = 300 Hz
|
|
*
|
|
DFN 82 98 DNOISE
|
|
VFN 82 98 DC 0.6551
|
|
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
|
|
RFN 83 98 1
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
Q3 451 41 99 POUT
|
|
RB1 40 41 1.5E+03
|
|
EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0;
|
|
Q4 451 43 50 NOUT
|
|
RB2 42 43 2.0E+03
|
|
EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0;
|
|
Lout 45 451 10E-10
|
|
RZ 45 453 100
|
|
CZ 453 12 4.67E-12
|
|
*
|
|
GSY 99 50 POLY(1) (99 50) 106.2E-6 -0.89E-06
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
|
|
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,IK=6E+00,BR=15,VAR=14.4, RC=30)
|
|
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,IK=11E+00,BR=30, VAR=20.0, RC=7)
|
|
.MODEL DW D(IS=1E-18)
|
|
.MODEL DX D()
|
|
.MODEL DY D(IS=1E-9)
|
|
.MODEL DZ D(IS=1E-6)
|
|
.MODEL DNOISE D(IS=1E-14,RS=0,KF=8.640E-12)
|
|
*
|
|
.SUBCKT Diac1 1 2
|
|
Done 1 3 DZ42hh
|
|
Dtwo 2 3 DZ42hh
|
|
.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9)
|
|
.ENDS Diac1
|
|
*
|
|
*
|
|
.ENDS ADA4091
|
|
*
|
|
* ADA4092 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 4X
|
|
* Developed by: HH / AD-SJ
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 05/14/2014 - Ported to Simplis (JSW)
|
|
* 0.0 (12/2010)
|
|
* Copyright 2010, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT ADA4092 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
Q1 6 4 7A QP
|
|
Q2 5 3 7B QP
|
|
RE1 7A 7 5.656E+02
|
|
RE2 7B 7 5.656E+02
|
|
I1 99 7 8.00E-06
|
|
D1 3 99 DX
|
|
D2 4 99 DX
|
|
D3 50 3 DX
|
|
D4 50 4 DX
|
|
D5 3 4 DX
|
|
D6 4 3 DX
|
|
R1 3 8 5E+03
|
|
R2 4 2 5E+03
|
|
R3 5 50 7.500E4;
|
|
R4 6 50 7.500E4;
|
|
Cph 5 5A 0.23E-12
|
|
Rph 5A 6 300
|
|
EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -1.4E-03 1 1 1 1
|
|
IOS 3 4 -2.0E-09
|
|
CDiff 1 2 2.5E-12
|
|
Cin1 1 50 2E-12
|
|
Cin2 2 50 2E-12
|
|
*
|
|
* INPUT PROTECTION NETWORK
|
|
*
|
|
X_in1 1 50 Diac1
|
|
X_in2 2 50 Diac1
|
|
X_in3 1 99 Diac1
|
|
X_in4 2 99 Diac1
|
|
*
|
|
*
|
|
RS1 99 39 400.0E3
|
|
RS2 39 50 400.0E3
|
|
EREF 98 0 (39,0) 1
|
|
*
|
|
* 1ST GAIN STAGE
|
|
*
|
|
R7 9 98 3.266E+08
|
|
G1 9 98 (6,5) 4.303E-06
|
|
D7 9 13 DX
|
|
D8 14 9 DX
|
|
V1 13 98 0.37; sink
|
|
V2 14 98 +0.017; source
|
|
*
|
|
* 2ND GAIN STAGE AND DOMINANT POLE
|
|
*
|
|
R8 12 98 1.0E+06
|
|
G2 12 98 (98,9) 1.0E-06
|
|
*
|
|
* Provision for second pole
|
|
*
|
|
G3 18 98 (98,12) 1E-05
|
|
R11 18 98 1E5
|
|
*
|
|
* CMRR
|
|
*
|
|
ECM 21 98 POLY(2) (1,98) (2,98) 0 7.813E-02 7.813E-02
|
|
R10 21 22 2.487E+04
|
|
R20 22 98 1.592E+01
|
|
C10 21 22 1E-9
|
|
*
|
|
* PSRR
|
|
*
|
|
EPSY 72 98 POLY(1) (99,50) +0.1E-6 1.485E+01
|
|
RPS1 72 73 5.305E+02
|
|
RPS2 73 98 3.183E-03
|
|
CPS1 72 73 1.00E-06
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 25.5E-3
|
|
HN 81 98 VN1 3.0E+01
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER
|
|
*
|
|
DFN 82 98 DNOISE
|
|
VFN 82 98 DC 0.6551
|
|
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
|
|
RFN 83 98 1
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
Q3 451 41 99 POUT
|
|
RB1 40 41 1.5E+03
|
|
EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0;
|
|
Q4 451 43 50 NOUT
|
|
RB2 42 43 2.0E+03
|
|
EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0;
|
|
Lout 45 451 6.2E-12
|
|
RZ 451 453 100
|
|
CZ 453 9 4.6E-12
|
|
*
|
|
GSY 99 50 POLY(1) (99 50) 79.9E-6 -1.04E-06
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
|
|
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130, BR=3,VAR=15, RC=38);
|
|
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250, BR=7, VAR=20, RC=8);
|
|
.MODEL DW D(IS=1E-18)
|
|
.MODEL DX D()
|
|
.MODEL DY D(IS=1E-9)
|
|
.MODEL DZ D(IS=1E-6)
|
|
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.15E-12)
|
|
*
|
|
.SUBCKT Diac1 1 2
|
|
Done 1 3 DZ42hh
|
|
Dtwo 2 3 DZ42hh
|
|
.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9)
|
|
.ENDS Diac1
|
|
.ENDS ADA4092
|
|
*
|
|
*
|
|
|
|
|
|
|
|
|
|
* ADA4096 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 3/30V, BIP, OP, OVP, RRIO, 2X
|
|
* Developed by: HH / AD-SJ
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 0.0 (07/2011)
|
|
* Copyright 2011, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT ADA4096 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
I1 99 7 8.00E-06
|
|
RE1 7 7A 3.714E+03
|
|
RE2 7 7B 3.714E+03
|
|
Q1 6 4 7A QP
|
|
Q2 5 3 7B QP
|
|
D1 3 99 DX
|
|
D2 4 99 DX
|
|
D3 50 3 DX
|
|
D4 50 4 DX
|
|
D5 3 4 DX
|
|
D6 4 3 DX
|
|
R1 202 8 5E-03
|
|
R2 204 4 5E-03
|
|
R3 5 50 7.500E4;
|
|
R4 6 50 7.500E4;
|
|
Cph 5 5A 6.3E-13
|
|
Rph 5A 6 400
|
|
EOS 8 3 POLY(4) (73,98) (22,98) (81,98) (83,98) -250E-06 1 1 1 1
|
|
IOS 3 4 -1.0E-09
|
|
CDiff 1 2 6.35E-12
|
|
Cin1 1 50 0.67E-12
|
|
Cin2 2 50 0.67E-12
|
|
*
|
|
* INPUT PROTECTION NETWORK
|
|
*
|
|
J1 1 201 202 JXB ;
|
|
J2 201 201 202 JXL ;
|
|
J3 2 203 204 JXB ;
|
|
J4 203 203 204 JXL
|
|
*
|
|
* 1ST GAIN STAGE
|
|
*
|
|
G1 9 98 (6,5) 1.0E-06
|
|
R7 9 98 1E6
|
|
*
|
|
* 2ND GAIN STAGE AND DOMINANT POLE
|
|
*
|
|
G2 12 98 (98,9) 3.375E-06
|
|
R8 12 98 3.4E+08
|
|
D7 12 13 DX
|
|
D8 14 12 DX
|
|
V1 13 98 +0.5;
|
|
V2 14 98 -0.2;
|
|
*
|
|
* Provision for second pole
|
|
*
|
|
G3 18 98 (98,12) 1E-05
|
|
R11 18 98 1E5
|
|
C11x 18 98 1E-14
|
|
*
|
|
* CMRR
|
|
*
|
|
ECM 21 98 POLY(2) (1,98) (2,98) 0 2.635E-01 2.635E-01
|
|
R10 21 22 1.326E+05
|
|
R20 22 98 7.958E+00
|
|
C10 21 22 1E-9
|
|
*
|
|
* PSRR
|
|
*
|
|
EPSY 72 98 POLY(1) (99,50) -1.514E+3 5.048E+01
|
|
RPS1 72 73 1.592E+03
|
|
RPS2 73 98 1.989E-03
|
|
CPS1 72 73 1.00E-06
|
|
*
|
|
* VOLTAGE NOISE REFERENCE
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 96.300E-3
|
|
HN 81 98 VN1 2.397E+01
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER
|
|
*
|
|
DFN 82 98 DNOISE 1000
|
|
IFN 98 82 DC 1E-03
|
|
DFN2 182 98 DY
|
|
IFN2 98 182 DC 1E-06
|
|
GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01
|
|
RFN 83 98 1
|
|
*
|
|
* Current Noise
|
|
D60 60 98 DN1 1000
|
|
I60 98 60 1E-03
|
|
D61 61 98 DN4
|
|
I61 98 61 1E-06
|
|
G60 1 50 61 60 1.23E-05
|
|
G61 2 50 61 60 1.33E-05
|
|
*
|
|
RS1 99 39 400.0E3
|
|
RS2 39 50 400.0E3
|
|
EREF 98 0 (39,0) 1
|
|
*
|
|
GSY 99 50 POLY(1) (99 50) -23.8E-6 -1.109E-06
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
Q3 451 41 99 POUT
|
|
RB1 40 41 4.37E+03
|
|
EB1 99 40 POLY(1) (98,18) 6.218E-01 1E-0;
|
|
Q4 451 43 50 NOUT
|
|
RB2 42 43 10E+03
|
|
EB2 42 50 POLY(1) (18,98) 6.170E-01 1E-0;
|
|
Lout 45 451 10E-10
|
|
EZ 453 98 (45 98) 1
|
|
CZ 453 12 4.94E-12
|
|
R99T 201 202 450k
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL QP PNP(BF=300, IS=1.00E-16, VA=130)
|
|
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,BR=4.3,VAR=20, RC=75);
|
|
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,BR=9.5, VAR=18, RC=42);
|
|
.MODEL DN1 D IS=1E-16
|
|
.MODEL DN4 D IS=1E-16 AF=1 KF=4.35E-17
|
|
.MODEL DW D(IS=1E-18)
|
|
.MODEL DX D(IS=1E-16)
|
|
.MODEL DY D(IS=1E-16,RS=0.1)
|
|
.MODEL DZ D(IS=1E-6)
|
|
.MODEL DNOISE D(IS=1E-16,RS=0,KF=2.6E-13)
|
|
.MODEL JXL PJF(BETA=4E-05 VTO=-2.0 IS=1E-18 LAMBDA=0.008 RD=1E-1
|
|
+ RS=5E1 CGD=1E-12 CGS=1E-12)
|
|
.MODEL JXB PJF(BETA=10E-05 VTO=-1.6 IS=1E-19 LAMBDA=0.005 RD=1E-1 RS=1.41E3)
|
|
.ENDS ADA4096
|
|
*
|
|
|
|
|
|
|
|
|
|
|
|
*
|
|
*ADA4177 SPICE DMod model Typical values
|
|
* Description: Amplifier
|
|
* Generic Desc: 30V, BIP, OP, Low Noise, Low THD, Non-RRin, RRout
|
|
* Developed by: DB ADSJ/ KF ADGT
|
|
* Revision History: draft
|
|
* 0.0 (02/2015)
|
|
* Copyright 2015 by Analog Devices
|
|
*
|
|
* Refer to "README.DOC" file for License Statement. Use of this
|
|
* model indicates your acceptance of the terms and provisions in
|
|
* the License Statement.
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT ADA4177 1 2 99 50 45
|
|
*
|
|
*INPUT STAGE
|
|
*
|
|
Q1 15 7 60 NIX
|
|
Q2 6 2 61 NIX
|
|
IOS 1 2 1.75E-10
|
|
I1 5 50 77e-6
|
|
EOS 7 1 POLY(4) (14,98) (73,98) (81,98) (70,98) 20E-6 1 1 1 1
|
|
ROS 7 1 1E-3; for debugging
|
|
RC1 11 15 2.6E4
|
|
RC2 11 6 2.6E4
|
|
RE1 60 5 0.896E2
|
|
RE2 61 5 0.896E2
|
|
C1 15 6 4.25E-13
|
|
D1 50 9 DX
|
|
V1 5 9 DC 1.8
|
|
D10 99 10 DX
|
|
V6 10 11 1.3
|
|
*
|
|
*
|
|
|
|
* CMRR
|
|
*
|
|
ECM 13 98 POLY(2) (1,50) (2,50) 0 7.192E-4 7.192E-4
|
|
RCM1 13 14 2.15E4
|
|
RCM2 14 98 5.31E-3
|
|
CCM1 13 14 7.4E-10
|
|
*
|
|
* PSRR
|
|
*
|
|
EPSY 72 98 POLY(1) (99,50) -1.683 0.056
|
|
CPS3 72 73 1E-6
|
|
RPS3 72 73 7.9577E+1
|
|
RPS4 73 98 6.5915E-4
|
|
*
|
|
* EXTRA POLE AND ZERO
|
|
*
|
|
G1 21 98 (6,15) 26E-6
|
|
R1 21 98 9.8E4
|
|
R2 21 22 9E6
|
|
C2 22 98 1.7614E-12
|
|
D3 21 99 DX
|
|
D4 50 21 DX
|
|
*
|
|
* VOLTAGE NOISE
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 16.45E-3
|
|
HN 81 98 VN1 9.3
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE
|
|
*
|
|
D5 69 98 DNOISE
|
|
VSN 69 98 DC .60551
|
|
H1 70 98 VSN 30.85
|
|
RN 70 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
GSY 99 50 POLY(1) (99,50) 240E-6 1.7495E-10
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G2 98 25 (21,98) 1E-6
|
|
R5 25 98 9.9E7
|
|
CF 45 25 3.59E-12
|
|
V4 25 33 0.35
|
|
D7 51 33 DX
|
|
EVN 51 98 POLY(1) (50,99) 0 0.5
|
|
V3 32 25 0.35
|
|
D6 32 97 DX
|
|
EVP 97 98 POLY(1) (99,50) 0 0.5
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
Q3 45 41 99 POUT
|
|
Q4 45 43 50 NOUT
|
|
RB1 40 41 6.25E4
|
|
RB2 42 43 6.25E4
|
|
EB1 99 40 POLY(1) (98,25) 0.9153 1
|
|
EB2 42 50 POLY(1) (25,98) 0.9153 1
|
|
|
|
|
|
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL NIX NPN (BF=71429,IS=1E-16)
|
|
.MODEL POUT PNP (BF=200,VAF=50,BR=2,IS=1E-15,RC=10.00)
|
|
.MODEL NOUT NPN (BF=200,VAF=100,BR=2,IS=1E-15,RC=8)
|
|
.MODEL DX D(IS=1E-16, RS=5, KF=1E-15)
|
|
.MODEL DNOISE D(IS=1E-16,RS=0,KF=1.095E-14)
|
|
.ENDS ADA4177
|
|
*$
|
|
* ADA4522-4 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: HV, ZD, Low Noise, Non-RRin, RRout
|
|
* Developed by: JG ADGT / VW ADSJ
|
|
* Revision History:
|
|
* 05/18/2015 - initial release for dual
|
|
* 10/27/2015 - initial release for quad
|
|
* 0.0 (05/2015)
|
|
* Copyright 2015 by Analog Devices
|
|
* T=25�C
|
|
*
|
|
* Refer to "README.DOC" file for License Statement. Use of this
|
|
* model indicates your acceptance of the terms and provisions in
|
|
* the License Statement.
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT ADA4522 1 2 99 50 45
|
|
*#ASSOC Category=Op-amp symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
M1 4 7 8 8 PIX L=1E-6 W=1.18E-04
|
|
M2 6 2 8 8 PIX L=1E-6 W=1.18E-04
|
|
M3 14 7 18 18 NIX L=1E-6 W=1.18E-04
|
|
M4 16 2 18 18 NIX L=1E-6 W=1.18E-04
|
|
RD1 4 50 1.33E+04
|
|
RD2 6 50 1.33E+04
|
|
RD3 99 14 1.33E+04
|
|
RD4 99 16 1.33E+04
|
|
C1 4 6 6.7E-13
|
|
C2 14 16 6.7E-13
|
|
I1 99 8 3.00E-05
|
|
I2 18 50 3.00E-05
|
|
V1 99 9 2.113E+00
|
|
V2 19 50 1.203E-01
|
|
D1 8 9 DX
|
|
D2 19 18 DX
|
|
EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -9.1E-06 0.1 0.1 0.1 0.1
|
|
IOS 1 2 100E-12
|
|
V5 99 3 2.2
|
|
D5 1 3 DX
|
|
D6 50 1 DX
|
|
V6 99 100 2.2
|
|
D7 2 100 DX
|
|
D8 50 2 DX
|
|
Ccm1 1 50 35E-12
|
|
Ccm2 2 50 35E-12
|
|
Cdm 1 2 7.0E-12
|
|
*
|
|
*CMRR
|
|
*
|
|
E1 72 98 POLY(2) (1,98) (2,98) 0 5.25E-03 5.25E-03
|
|
R10 72 73 1.89E+02
|
|
R20 73 98 4.8E-01
|
|
C10 72 73 1.00E-06
|
|
*
|
|
* PSRR
|
|
*
|
|
EPSY 21 98 POLY(1) (99,50) -2.712E-00 2.4
|
|
RPS1 21 22 1.59E+05
|
|
RPS2 22 98 3.18E-01
|
|
CPS1 21 22 1.00E-06
|
|
*
|
|
*
|
|
* VOLTAGE NOISE REFERENCE
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 265E-05
|
|
HN 81 98 VN1 6.6E0
|
|
RNHH1 81 183 5.3
|
|
CHH1 183 98 1E-012
|
|
*
|
|
*BPF
|
|
*
|
|
EV5 83 98 VALUE = { V(203,98)+V(205,98) }
|
|
R94 204 98 300
|
|
L92 200 210 6.0e-006
|
|
C92 210 204 9e-011
|
|
R93 200 204 5.5E03
|
|
EV4 205 98 204 98 10.5
|
|
EV3 203 98 202 98 5.5
|
|
R92 202 98 200
|
|
L91 200 201 3.0e-005
|
|
C91 201 202 10e-010
|
|
R91 200 202 1E03
|
|
EV1 200 98 81 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
|
|
GSY 99 50 POLY(1) (99,50) 805.1E-06 -1.55E-9
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 POLY(2) (4,6) (14,16) 0 7.103E-03 7.103E-03
|
|
R1 30 98 1.00E+06
|
|
RZ 455 31 0.195E+00
|
|
CF 30 31 4.05E-9
|
|
EZ 455 98 (45,98) 1
|
|
V3 32 30 -7.5E-04
|
|
V4 30 33 -4.9E-04
|
|
D3 32 98 DX
|
|
D4 98 33 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 45 46 99 99 POX L=3E-6 W=20E-04
|
|
M6 45 47 50 50 NOX L=3E-6 W=40E-04
|
|
EG1 99 46 POLY(1) (98,30) 8.523E-01 1
|
|
EG2 47 50 POLY(1) (30,98) 8.523E-01 1
|
|
*EG1 99 46 POLY(1) (98,30) 8.523E-01 1
|
|
*EG2 47 50 POLY(1) (30,98) 8.523E-01 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.83,LAMBDA=0.047,RD=7)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=4.00E-05,VTO=+0.83,LAMBDA=0.047,RD=38)
|
|
.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047)
|
|
.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022)
|
|
.MODEL DX D(IS=1E-14,RS=0.1)
|
|
*
|
|
*
|
|
.ENDS ADA4522
|
|
*
|
|
*$
|
|
*ADA4610 Macro-model
|
|
*Function:Amplifier
|
|
*
|
|
*Revision History:
|
|
*Rev.2.1 Feb 2016-ZZ
|
|
*Copyright 2016 by Analog Devices
|
|
*
|
|
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
|
|
*for License Statement. Use of this model indicates your acceptance
|
|
*of the terms and provisions in the License Staement.
|
|
*
|
|
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
|
|
*
|
|
*Not modeled: Distortion, PSRR, Overload Recovery,
|
|
* Shutdown Turn On/Turn Off time
|
|
*
|
|
*Parameters modeled include:
|
|
* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
|
|
* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
|
|
* Capacitive load drive, Quiescent and dynamic supply currents,
|
|
* Shut Down pin functionality where applicable,
|
|
* Single supply & offset supply functionality.
|
|
*
|
|
*Node Assignments
|
|
* Non-Inverting Input
|
|
* | Inverting Input
|
|
* | | Positive supply
|
|
* | | | Negative supply
|
|
* | | | | Output
|
|
* | | | | |
|
|
.Subckt ADA4610 100 101 102 103 104
|
|
*#ASSOC Category="Op-Amps" symbol=opamp
|
|
***Power Supplies***
|
|
Rz1 102 1020 Rideal 1e-6
|
|
Rz2 103 1030 Rideal 1e-6
|
|
Ibias 1020 1030 dc 0.33e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 2.97e-3
|
|
S1 98 1030 106 113 Switch
|
|
R1 1020 99 Rideal 1e7
|
|
R2 99 1030 Rideal 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
S2 1 100 106 113 Switch
|
|
S3 9 101 106 113 Switch
|
|
VOS 1 2 dc 0.2e-6
|
|
IbiasP 110 2 dc 5e-12
|
|
IbiasN 110 9 dc 5e-12
|
|
RinCMP 110 2 Rideal 20000000000000e6
|
|
RinCMN 9 110 Rideal 20000000000000e6
|
|
CinCMP 110 2 5.7e-12
|
|
CinCMN 9 110 5.7e-12
|
|
IOS 9 2 2e-12
|
|
RinDiff 9 2 Rideal 20000000000000e3
|
|
CinDiff 9 2 2.2e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 Rideal 1e3
|
|
RX1 40 3 Rideal 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 2.96
|
|
VinN 42 112 dc 2.96
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.7071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.7071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.7071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.7071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 Rideal 1e12
|
|
RcmrrN 10 9 Rideal 1e12
|
|
g10 11 110 10 110 -1e-10
|
|
Lcmrr 11 12 1e-12
|
|
Rcmrr 12 110 Rideal 1e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
***Power Down***
|
|
VPD 111 80 dc 2
|
|
VPD1 81 0 dc 1.5
|
|
RPD 111 106 Rideal 0.286e6
|
|
ePD 80 113 82 0 1
|
|
RDP1 82 0 Rideal 1e3
|
|
CPD 82 0 1e-10
|
|
S5 81 82 83 113 Switch
|
|
CDP1 83 0 1e-12
|
|
RPD2 106 83 1e6
|
|
*
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 104 Rideal 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 Rideal 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 350 Hz***
|
|
g210 210 110 200 110 0.3502e-6
|
|
R210 210 110 Rideal 454.73e6
|
|
C210 210 110 1e-012
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 Rideal 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 5.709
|
|
VoutN 64 66 dc 5.428
|
|
e60 65 110 111 110 1.34
|
|
e61 66 110 112 110 1.34
|
|
*
|
|
*
|
|
***Pole-Zero at 84KHz, 180KHz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 Rideal 1000
|
|
R221 220 221 Rideal 0.875e3
|
|
C220 221 110 1010.5064e-12
|
|
*
|
|
***Pole at 110MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 Rideal 1000
|
|
C230 230 110 1.4469e-12
|
|
*
|
|
***Buffer***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 Rideal 1000
|
|
*
|
|
***Notch: f=2.2MHz, Zeta=1.2, Gain=0.8dB***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 Rideal 10
|
|
L280 285 281 3425.757e-9
|
|
C280 281 282 1527.698e-12
|
|
R281 282 110 Rideal 103.65
|
|
*
|
|
***Peak: f=0.5MHz, Zeta=3.1, Gain=5.1dB***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 Rideal 10
|
|
L290 290 291 513.402e-9
|
|
C290 291 292 197351.907e-12
|
|
R291 292 110 Rideal 12.518
|
|
e295 295 110 292 110 1.7989
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 Rideal 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 Rideal 163
|
|
Lout 303 310 80e-9
|
|
Cout 310 110 6e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc 5.736
|
|
VIoutN 304 306 dc 5.736
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 Rideal 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 0.785
|
|
VoutN1 74 112 dc 0.785
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 Rideal 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 Rideal 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc 102 314 diode
|
|
RX5 311 312 Rideal 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 Rideal 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 103 diode
|
|
*
|
|
*
|
|
***Output Switch***
|
|
S4 104 313 106 113 Switch
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=174.665)
|
|
.model DzSlewN D(BV=174.665)
|
|
.model DVnoisy D(IS=2.03e-15 KF=8.16e-18)
|
|
.model DINnoisy D(IS=1.45e-22 KF=8.13e-18)
|
|
.model DIPnoisy D(IS=1.45e-22 KF=8.13e-18)
|
|
.model Rideal res(T_ABS=-273)
|
|
*
|
|
.ends ADA4610
|
|
* AD4622 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 30V, JFET, OP, S SPLY, RRO
|
|
* Developed by: DB / ADSJ
|
|
* Revision History:
|
|
* 1.0 (11/2015)
|
|
* 2.0 (12/2017)
|
|
* 12/01/2017 - corrected pin order to standard by AR / ADGT
|
|
* Copyright 2015 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
*
|
|
* Notes: This model simulates typical values @ Vsy=�15V, T=25�C.
|
|
* Ibias and Vos are static and will not vary with Vcm.
|
|
* Distortion is not modelled.
|
|
* (ada4622 DMod model)
|
|
*
|
|
* Usage:-
|
|
|
|
*X1 3 2 7 4 6 ADA4622
|
|
* | | | | |
|
|
* | | | | Output
|
|
* | | | Negative Supply
|
|
* | | Positive Supply
|
|
* | Inverting Input
|
|
* Non-Inverting Input
|
|
|
|
.SUBCKT ADA4622 3 2 7 4 6
|
|
|
|
* Input Impedances
|
|
|
|
I1 0 3 1.000E-012
|
|
I2 0 2 1.000E-012
|
|
R3 3 2 1.333E+013
|
|
R4 3 0 2.000E+013
|
|
R5 2 0 2.000E+013
|
|
C1 3 0 1.800E-012
|
|
C2 2 0 1.800E-012
|
|
C3 3 2 4.000E-013
|
|
|
|
* Preconditioning Gain Stage and Sum Node for
|
|
* Transconductance Control and Noise Insertion
|
|
|
|
G1 0 41 POLY(2) 3 2 60 63 0.000E+000 2.377E-003 1.947E-003
|
|
|
|
* Limiting Section for Slew-Rate Control
|
|
|
|
D5 41 43 DL
|
|
V1 43 0 1.082E+002
|
|
D6 42 41 DL
|
|
V2 0 42 8.170E+001
|
|
G2 41 0 41 0 1.0E-5
|
|
E6 20 0 POLY(1) 41 0 0 1
|
|
+0 -6.562164E-006 0 -5.302485E-012
|
|
+0 3.817254E-016 0 -1.371241E-021
|
|
|
|
.MODEL DL D IS=1E-18 EG=0.1 N=0.2
|
|
|
|
* Second-Order Frequency Shaping
|
|
|
|
R50 20 21 5
|
|
C50 21 0 1.224E-009
|
|
R52 21 23 35
|
|
C51 23 0 5.350E-011
|
|
R54 23 25 245
|
|
C52 25 0 7.642E-012
|
|
R56 25 27 1715
|
|
C53 27 0 1.031E-012
|
|
R58 27 40 12005
|
|
C54 40 0 1.105E-013
|
|
|
|
* Primary Gain Block and Dominant Pole/Zero
|
|
|
|
G3 0 44 POLY(3) 45 6 40 0 0 54 0 -1.033E-003 1E-5 5E-4
|
|
G4 44 0 44 0 1.981E-011
|
|
C4 44 4 4.348E-013
|
|
|
|
* Output Stage and Swing Limiting Network
|
|
|
|
E2 46 0 POLY(1) 7 0 -1.178E+000 1.000E+002
|
|
E3 47 0 POLY(1) 4 0 2.801E-001 1.000E+002
|
|
D7 44 46 DL
|
|
D8 47 44 DL
|
|
G7 45 6 45 6 100
|
|
E5 55 0 6 0 1.00E+002
|
|
C5 55 50 4.348E-013
|
|
R7 50 44 1.150E+005
|
|
E4 53 0 45 6 2.863E+005
|
|
V7 53 56 7.734E+001
|
|
D9 56 54 DL
|
|
V8 57 53 100.2
|
|
D10 54 57 DL
|
|
G5 54 0 54 0 9.1E-6
|
|
G8 45 7 POLY(2) 7 0 0 44 0 2.500E-002 2.500E-004
|
|
G9 45 4 POLY(2) 4 0 0 44 0 2.500E-002 2.500E-004
|
|
R12 7 45 4.000E+001
|
|
R13 4 45 4.000E+001
|
|
G10 58 59 POLY(2) 0 45 44 0 0 2.500E-002 2.500E-004
|
|
G11 51 0 51 0 100
|
|
G12 52 0 52 0 100
|
|
G13 4 7 POLY(2) 51 0 52 0 0 100 100
|
|
D11 59 0 DX
|
|
D12 51 59 DX
|
|
D13 52 58 DX
|
|
D14 58 0 DX
|
|
R10 58 0 7.00E+003
|
|
R11 59 0 7.00E+003
|
|
|
|
.MODEL DX D IS=1E-14 EG=0.6
|
|
|
|
* Quiescent Supply Current c
|
|
|
|
I9 7 4 6.650E-004
|
|
|
|
* Noise Modeling
|
|
|
|
D60 60 0 DN1 1000
|
|
I60 0 60 1E-3
|
|
D63 63 0 DN2
|
|
I63 0 63 1E-6
|
|
|
|
.MODEL DN1 D IS=1E-16
|
|
.MODEL DN2 D IS=1E-16 AF=1 KF=7.715E-018
|
|
|
|
.ENDS ADA4622
|
|
*ADA4625 Macro-model
|
|
*Function:Amplifier
|
|
*
|
|
*Revision History:
|
|
*Rev.1 Oct 2017-JL
|
|
*Copyright 2017 by Analog Devices
|
|
*
|
|
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
|
|
*for License Statement. Use of this model indicates your acceptance
|
|
*of the terms and provisions in the License Staement.
|
|
*
|
|
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
|
|
*
|
|
*Not modeled: Distortion, PSRR, Overload Recovery,
|
|
* Shutdown Turn On/Turn Off time
|
|
*
|
|
*Parameters modeled include:
|
|
* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
|
|
* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
|
|
* Capacitive load drive, Quiescent and dynamic supply currents,
|
|
* Shut Down pin functionality where applicable,
|
|
* Single supply & offset supply functionality.
|
|
*
|
|
*Node Assignments
|
|
* Non-Inverting Input
|
|
* | Inverting Input
|
|
* | | Positive supply
|
|
* | | | Negative supply
|
|
* | | | | Output
|
|
* | | | | |
|
|
.Subckt ADA4625 IN+ IN- V+ V- OUT
|
|
*
|
|
***Power Supplies***
|
|
Rz1 V+ 1020 Rideal 1e-6
|
|
Rz2 V- 1030 Rideal 1e-6
|
|
Ibias 1020 1030 dc 0.4e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 3.6e-3
|
|
S1 98 1030 106 113 Switch
|
|
R1 1020 99 Rideal 1e7
|
|
R2 99 1030 Rideal 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
S2 1 IN+ 106 113 Switch
|
|
S3 9 IN- 106 113 Switch
|
|
VOS 1 2 dc 15e-6
|
|
IbiasP 110 2 dc 15e-12
|
|
IbiasN 110 9 dc 15e-12
|
|
RinCMP 110 2 Rideal 1000000e6
|
|
RinCMN 9 110 Rideal 1000000e6
|
|
CinCMP 110 2 11.3e-12
|
|
CinCMN 9 110 11.3e-12
|
|
IOS 9 2 2e-12
|
|
RinDiff 9 2 Rideal 1000000000e3
|
|
CinDiff 9 2 8.6e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 Rideal 1e3
|
|
RX1 40 3 Rideal 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 3.96
|
|
VinN 42 112 dc 0.26
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.7071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.7071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.7071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.7071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 Rideal 1e12
|
|
RcmrrN 10 9 Rideal 1e12
|
|
g10 11 110 10 110 -0.634e-9
|
|
Lcmrr 11 12 1591.6e-3
|
|
Rcmrr 12 110 Rideal 1e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
***Power Down***
|
|
VPD 111 80 dc 2.6
|
|
VPD1 81 0 dc 0.1
|
|
RPD 111 106 Rideal 1e6
|
|
ePD 80 113 82 0 1
|
|
RDP1 82 0 Rideal 1e3
|
|
CPD 82 0 1e-10
|
|
S5 81 82 83 113 Switch
|
|
CDP1 83 0 1e-12
|
|
RPD2 106 83 1e6
|
|
*
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 OUT Rideal 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 Rideal 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 0.599999999999996 Hz***
|
|
g210 210 110 200 110 0.3455e-6
|
|
R210 210 110 Rideal 265.26e6
|
|
C210 210 110 1e-012
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 Rideal 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 5.723
|
|
VoutN 64 66 dc 5.603
|
|
e60 65 110 111 110 1.004
|
|
e61 66 110 112 110 1.004
|
|
*
|
|
*
|
|
***Pole at 300MHz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 Rideal 1000
|
|
C220 220 110 0.5305e-12
|
|
*
|
|
***Pole at 300MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 Rideal 1000
|
|
C230 230 110 0.5305e-12
|
|
*
|
|
***Buffer***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 Rideal 1000
|
|
*
|
|
***Buffer***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 Rideal 10
|
|
*
|
|
***Buffer***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 Rideal 10
|
|
e295 295 110 292 110 1
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 Rideal 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 Rideal 2
|
|
Lout 303 310 1e-9
|
|
Cout 310 110 1e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc 3.936
|
|
VIoutN 304 306 dc 3.936
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 Rideal 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 0.965
|
|
VoutN1 74 112 dc 0.945
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 Rideal 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 Rideal 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc V+ 314 diode
|
|
RX5 311 312 Rideal 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 Rideal 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 V- diode
|
|
*
|
|
*
|
|
***Output Switch***
|
|
S4 OUT 313 106 113 Switch
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model Switch vswitch(Von=0.105,Voff=0.095,ron=0.001,roff=1e6)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=139.423)
|
|
.model DzSlewN D(BV=139.423)
|
|
.model DVnoisy D(IS=4.11e-16 KF=3.28e-18)
|
|
.model DINnoisy D(IS=7.72e-22 KF=0.00e0)
|
|
.model DIPnoisy D(IS=7.72e-22 KF=0.00e0)
|
|
.model Rideal res(T_ABS=-273)
|
|
*
|
|
.ends ADA4625
|
|
|
|
* ADA4627 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 8/30V, JFET, OP, Low Noise, Low Ib, 1X
|
|
* Developed by: HH / ADSJ
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (07/2009)
|
|
* Copyright 2009, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
* CAUTION!! To aid in convergence, most Spice simulators add a
|
|
* conductance on every node to insure that no node is floating.
|
|
* This is GMIN, and the default value is usually 1E-12. To properly
|
|
* simulate the low input bias current and low current noise, the
|
|
* Spice simulator options have to be set to the following:
|
|
* .OPTIONS GMIN=0.01p
|
|
* .OPTIONS ABSTOL=0.01pA
|
|
* .OPTIONS ITL1=500
|
|
* .OPTIONS ITL2=200
|
|
* .OPTIONS ITL4=100
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT ADA4627 1 2 99 50 30
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
Cdiff 1 2 4.7E-12
|
|
Cin1 1 50 7.5E-12
|
|
Cin2 2 50 7.5E-12
|
|
*
|
|
R3 5 99 1.478E+03
|
|
R4 6 99 1.478E+03
|
|
J1 5 2 4 JX
|
|
J2 6 7 4 JX
|
|
*
|
|
I1 4 50 2.70E-03
|
|
DI1 4a 4 DX
|
|
VI1 4a 50 5.5V
|
|
IOS 1 2 0.25E-12
|
|
EOS 60 1 POLY(2) (17,24) (73,98) 110E-6 1 1
|
|
EN 7 60 42 0 1
|
|
*
|
|
EREF 98 0 24 0 1
|
|
*
|
|
* SECOND STAGE
|
|
*
|
|
R5 9 98 4.097E+05
|
|
C3 9 98 3.850E-09
|
|
G1 98 9 5 6 7.700E-02
|
|
V2 99 8 2.86
|
|
V3 10 50 2.41;
|
|
D1 9 8 DX
|
|
D2 10 9 DX
|
|
*
|
|
* 2nd POLE
|
|
*
|
|
R13 18 98 1.000E+03
|
|
C9 18 98 1.0E-14
|
|
G5 98 18 9 24 1E-3
|
|
*
|
|
* COMMON-MODE GAIN NETWORK
|
|
*
|
|
R11 16 17 2.698E-01
|
|
R12 17 98 1.326E-04
|
|
E3 16 98 POLY(2) 1 98 2 98 0 8.459E-03 8.459E-03
|
|
C8 16 17 100E-6
|
|
*
|
|
* PSRR NETWORK
|
|
*
|
|
EPSY 98 72 POLY(1) (99,50) 3.350E-03 1.005E-01
|
|
CPS3 72 73 1.000E-09
|
|
RPS3 72 73 9.947E+05
|
|
RPS4 73 98 1.326E+02
|
|
*
|
|
* VOLTAGE NOISE GENERATOR
|
|
*
|
|
VN1 41 0 DC 2
|
|
DN1 41 42 DEN
|
|
DN2 42 43 DEN
|
|
VN2 0 43 DC 2
|
|
*
|
|
* CURRENT NOISE GENERATOR
|
|
*
|
|
VN3 44 0 DC 2
|
|
DN3 44 45 DIN
|
|
DN4 45 46 DIN
|
|
VN4 0 46 DC 2
|
|
*
|
|
* CURRENT NOISE GENERATOR
|
|
*
|
|
VN5 47 0 DC 2
|
|
DN5 47 48 DIN
|
|
DN6 48 49 DIN
|
|
VN6 0 49 DC 2
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R14 24 99 500E3
|
|
R15 24 50 500E3
|
|
GSY 99 50 POLY(1) (99,50) 4.079E-03 2.985E-06
|
|
R16 29 99 100
|
|
R17 29 50 100
|
|
G6 27 50 18 29 10.0E-3
|
|
G7 28 50 29 18 10.0E-3
|
|
G8 29 99 POLY(1) 99 18 1E-16 1.00E-2
|
|
G9 50 29 POLY(1) 18 50 1E-16 1.00E-2
|
|
*
|
|
V4 25 29 1.99; Isc high side
|
|
V5 29 26 2.4
|
|
D3 18 25 DX
|
|
D4 26 18 DX
|
|
*
|
|
D5 99 27 DX
|
|
D6 99 28 DX
|
|
D7 50 27 DY
|
|
D8 50 28 DY
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
L1 29 30a 1E-15
|
|
R24 30a 30 1m
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX NJF(BETA=3.400E-03 VTO=-1.500 IS=7E-13 RD=1
|
|
+ RS=1 CGD=1.5E-12 CGS=1.5E-12 )
|
|
*.MODEL JX PJF(BETA=1.4E-3 VTO=-1.000 IS=20E-12 RD=0
|
|
*+ RS=0 CGD=3E-12 CGS=3E-12)
|
|
.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12)
|
|
.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
|
|
.MODEL DEN D(IS=1E-12 RS=1.7E3, KF=6.53E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1)
|
|
*
|
|
.ENDS ADA4627
|
|
$
|
|
|
|
|
|
|
|
|
|
* ADTL082 SPICE Macro-model Typical Values
|
|
* Description: Amplifier
|
|
* Generic Desc: Industry Standard TL082
|
|
* Developed by: ADSJ -- SS
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 ( 06/2007)
|
|
* Copyright 2007, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
* This model simulates typical value parameters at Vs=�13V
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT ADTL082 1 2 99 50 30
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
R3 5 50 6.437E+03
|
|
R4 6 50 6.437E+03
|
|
CIN 1 2 5.5E-12
|
|
I1 99 4 9.321E-04
|
|
IOS 1 2 1.00E-12
|
|
EOS 60 1 POLY(2) (17,24) (73,24) 2.00E-03 1 1
|
|
EN 7 60 POLY(1) (81, 98) 0 1
|
|
J1 5 2 4 JX
|
|
J2 6 7 4 JX
|
|
GB1 2 50 POLY(3) (4,2) (5,2) (50,2) 0 1E-12 1E-12 1E-12
|
|
GB2 7 50 POLY(3) (4,7) (6,7) (50,7) 0 1E-12 1E-12 1E-12
|
|
*
|
|
EREFNEG 1000 0 24 0 -1
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
*
|
|
* VOLTAGE NOISE GENERATOR
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 17.1E-3
|
|
HN 81 98 VN1 1.6E1
|
|
RN2 81 98 1
|
|
|
|
* Flicker noise
|
|
*
|
|
*D10 69 98 DNOISE
|
|
*VSN 69 98 DC .6551
|
|
*H1 70 98 VSN 8.22E+01
|
|
*RN 70 98 1
|
|
|
|
|
|
** SECOND STAGE & POLE AT 1.3 kHZ
|
|
*
|
|
R5 9 98 1.48E+05
|
|
C3 9 98 39000E-12
|
|
G1 98 9 5 6 1.30E-01
|
|
V2 99 8 0.7
|
|
V3 10 1000 -10.2
|
|
|
|
D1 9 8 DX
|
|
D2 10 9 DX
|
|
*
|
|
* COMMON-MODE GAIN NETWORK
|
|
*
|
|
E3 16 98 POLY(2) (1,98) (2,98) 0 2.623E-03 2.623E-03
|
|
R11 16 17 1.326E+06
|
|
R12 17 98 3.183E+03
|
|
C8 16 17 100E-12
|
|
*E3 16 98 POLY(2) (1,98) (2,98) 0 1.0E-02 1.0E-02
|
|
*R11 16 17 3.27E+02
|
|
*R12 17 98 1.59E-1
|
|
*C8 16 17 50E-8
|
|
*
|
|
* PSRR NETWORK
|
|
*
|
|
EPSY 98 72 POLY(1) (99,50) 0 30.00E-02
|
|
CPS3 72 73 300E-12
|
|
RPS3 72 73 20.0E+05
|
|
RPS4 73 98 1.96E+02; was 1.96E+02
|
|
*
|
|
* POLE AT 15 MHZ
|
|
*
|
|
R13 18 98 1E3
|
|
C9 18 98 1.48E-11
|
|
G5 98 18 9 24 1E-3
|
|
*
|
|
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R14 24 99 500E3
|
|
R15 24 50 500E3
|
|
CF 24 0 1E-6
|
|
GSY 99 50 POLY(1) 99 50 .0002 1.0E-6
|
|
R16 29 99 8.00E+01
|
|
R17 29 50 8.00E+01
|
|
L1 29 30 1E-8
|
|
G6 27 50 18 29 1.25E-02
|
|
G7 28 50 29 18 1.25E-02
|
|
G8 29 99 99 18 1.25E-02
|
|
G9 50 29 18 50 1.25E-02
|
|
V4 25 29 0.675
|
|
V5 29 26 0.675
|
|
D3 18 25 DX
|
|
D4 26 18 DX
|
|
D5 99 27 DX
|
|
D6 99 28 DX
|
|
D7 50 27 DY
|
|
D8 50 28 DY
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL JX PJF(BETA=1.4E-3 VTO=-1.000 IS=20E-12 RD=0
|
|
+ RS=0 CGD=1E-12 CGS=1E-12)
|
|
.MODEL DX D(IS=1E-12 RS=0 CJO=1E-12)
|
|
.MODEL DY D(IS=1E-12 BV=50 RS=10 CJO=1E-12)
|
|
.MODEL DEN D(IS=1E-12 RS=200 KF=2.651E-15 AF=6.8E-14)
|
|
.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1)
|
|
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.6E-16)
|
|
*
|
|
*
|
|
.ENDS ADTL082
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* OP1177 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 5/30V, BIP, OP, Low Vos, Low Ib, 1X
|
|
* Developed by: SB, ADSiV apps
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (05/2002)
|
|
* Copyright 2002, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include: Vsy=�15V
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP1177 1 2 99 50 34
|
|
*
|
|
* INPUT STAGE & POLE AT 100 MHZ
|
|
*
|
|
R3 5 51 6.8E3
|
|
R4 6 51 6.8E3
|
|
CIN 1 2 1.5E-12
|
|
C2 5 6 3.5E-12
|
|
I1 97 4 500E-6
|
|
IOS 1 2 0.1E-9
|
|
EOS 9 3 POLY(2) (26, 28) (73, 98) 15E-6 1 1
|
|
Q1 5 2 7 QX
|
|
Q2 6 9 8 QX
|
|
R5 7 4 50
|
|
R6 8 4 50
|
|
D1 2 36 DZ
|
|
D2 1 36 DZ
|
|
EN 3 1 10 0 1
|
|
GN1 0 2 13 0 1
|
|
GN2 0 1 16 0 1
|
|
*
|
|
EREF 98 0 28 0 1
|
|
EP 97 0 99 0 1
|
|
EM 51 0 50 0 1
|
|
*
|
|
* VOLTAGE NOISE SOURCE
|
|
*
|
|
DN1 35 10 DEN
|
|
DN2 10 11 DEN
|
|
VN1 35 0 DC 2
|
|
VN2 0 11 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN3 12 13 DIN
|
|
DN4 13 14 DIN
|
|
VN3 12 0 DC 2
|
|
VN4 0 14 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN5 15 16 DIN
|
|
DN6 16 17 DIN
|
|
VN5 15 0 DC 2
|
|
VN6 0 17 DC 2
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT 0.439 HZ
|
|
*
|
|
R7 18 98 1.45E7
|
|
C3 18 98 25E-9
|
|
G1 98 18 5 6 5.15E-3
|
|
V2 97 19 1.5
|
|
V3 20 51 1.5
|
|
D3 18 19 DX
|
|
D4 20 18 DX
|
|
*
|
|
* POLE/ZERO PAIR AT 1.5MHz/12.7MHz
|
|
*
|
|
R8 21 98 1E3
|
|
R9 21 22 1.25E3
|
|
C4 22 98 10E-12
|
|
G2 98 21 18 28 1E-3
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R10 23 98 1
|
|
C5 23 98 62E-12
|
|
G3 98 23 21 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R11 24 98 1
|
|
C6 24 98 62E-12
|
|
G4 98 24 23 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R14 27 98 1
|
|
C8 27 98 62E-12
|
|
G5 98 27 24 28 1
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ
|
|
*
|
|
R12 25 26 1E6
|
|
C7 25 26 159.155E-12
|
|
R13 26 98 1
|
|
E2 25 98 POLY(2) 1 98 2 98 0 0.28 0.28
|
|
*
|
|
*PSRR=121dB
|
|
EPSY 98 72 POLY(1) (99,50) 0 1
|
|
RPS3 72 73 1E6
|
|
CPS3 72 73 3E-9
|
|
RPS4 73 98 1
|
|
|
|
* OUTPUT STAGE
|
|
*
|
|
R15 28 99 100E3
|
|
R16 28 50 100E3
|
|
C9 28 50 1E-6
|
|
ISY 99 50 250E-6
|
|
R17 29 99 100
|
|
R18 29 50 100
|
|
L2 29 34 1E-9
|
|
G6 32 50 27 29 10E-3
|
|
G7 33 50 29 27 10E-3
|
|
G8 29 99 99 27 10E-3
|
|
G9 50 29 27 50 10E-3
|
|
V4 30 29 1.3
|
|
V5 29 31 3.8
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
D5 27 30 DX
|
|
D6 31 27 DX
|
|
D7 99 32 DX
|
|
D8 99 33 DX
|
|
D9 50 32 DY
|
|
D10 50 33 DY
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL QX PNP(BF=5E5)
|
|
.MODEL DX D(IS=1E-12)
|
|
.MODEL DY D(IS=1E-15 BV=50)
|
|
.MODEL DZ D(IS=1E-15 BV=7.0)
|
|
.MODEL DEN D(IS=1E-12 RS=6.8E3 KF=1.95E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1)
|
|
.ENDS OP1177
|
|
*$
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* OP213 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 2X
|
|
* Developed by: JCB / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (09/1992)
|
|
* Copyright 1992, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
*
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP213 3 2 7 4 6
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
R3 4 19 1.5E3
|
|
R4 4 20 1.5E3
|
|
C1 19 20 5.31E-12
|
|
I1 7 18 106E-6
|
|
IOS 2 3 25E-09
|
|
EOS 12 5 POLY(1) 51 4 25E-06 1
|
|
Q1 19 3 18 PNP1
|
|
Q2 20 12 18 PNP1
|
|
CIN 3 2 3E-12
|
|
D1 3 1 DY
|
|
D2 2 1 DY
|
|
EN 5 2 22 0 1
|
|
GN1 0 2 25 0 1E-5
|
|
GN2 0 3 28 0 1E-5
|
|
*
|
|
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
DN1 21 22 DEN
|
|
DN2 22 23 DEN
|
|
VN1 21 0 DC 2
|
|
VN2 0 23 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
DN3 24 25 DIN
|
|
DN4 25 26 DIN
|
|
VN3 24 0 DC 2
|
|
VN4 0 26 DC 2
|
|
*
|
|
* SECOND CURRENT NOISE SOURCE
|
|
*
|
|
DN5 27 28 DIN
|
|
DN6 28 29 DIN
|
|
VN5 27 0 DC 2
|
|
VN6 0 29 DC 2
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT .2000E+01 HZ
|
|
*
|
|
G2 34 36 19 20 2.65E-04
|
|
R7 34 36 39E+06
|
|
V3 35 4 DC 6
|
|
D4 36 35 DX
|
|
VB2 34 4 1.6
|
|
*
|
|
* SUPPLY/2 GENERATOR
|
|
*
|
|
ISY 7 4 0.2E-3
|
|
R10 7 60 40E+3
|
|
R11 60 4 40E+3
|
|
C3 60 0 1E-9
|
|
*
|
|
* CMRR STAGE & POLE AT 6 kHZ
|
|
*
|
|
ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8
|
|
CCM 50 51 26.5E-12
|
|
RCM1 50 51 1E6
|
|
RCM2 51 4 1
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R12 37 36 1E3
|
|
R13 38 36 500
|
|
C4 37 6 20E-12
|
|
C5 38 39 20E-12
|
|
M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
D5 39 47 DX
|
|
D6 47 45 DX
|
|
Q3 39 40 41 QPA 8
|
|
VB 7 40 DC 0.861
|
|
R14 7 41 375
|
|
Q4 41 7 43 QNA 1
|
|
R17 7 43 15
|
|
Q5 43 39 6 QNA 20
|
|
Q6 46 45 6 QPA 20
|
|
R18 46 4 15
|
|
Q7 36 46 4 QNA 1
|
|
M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9
|
|
*
|
|
* NONLINEAR MODELS USED
|
|
*
|
|
.MODEL DX D (IS=1E-15)
|
|
.MODEL DY D (IS=1E-15 BV=7)
|
|
.MODEL PNP1 PNP (BF=220)
|
|
.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1)
|
|
.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3
|
|
+ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573
|
|
+ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12
|
|
+ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
|
|
.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3
|
|
+ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13
|
|
+ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4
|
|
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
|
|
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
|
|
+ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
|
|
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4
|
|
+ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
|
|
*
|
|
.ENDS
|
|
|
|
|
|
|
|
|
|
|
|
* OP2177 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 5/30V, BIP, OP, Low Vos, Low Ib, 2X
|
|
* Developed by: SB, ADSiV apps
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (05/2002)
|
|
* Copyright 2002, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include: Vsy=�15V
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP2177 1 2 99 50 34
|
|
*
|
|
* INPUT STAGE & POLE AT 100 MHZ
|
|
*
|
|
R3 5 51 6.8E3
|
|
R4 6 51 6.8E3
|
|
CIN 1 2 1.5E-12
|
|
C2 5 6 3.5E-12
|
|
I1 97 4 500E-6
|
|
IOS 1 2 0.1E-9
|
|
EOS 9 3 POLY(2) (26, 28) (73, 98) 15E-6 1 1
|
|
Q1 5 2 7 QX
|
|
Q2 6 9 8 QX
|
|
R5 7 4 50
|
|
R6 8 4 50
|
|
D1 2 36 DZ
|
|
D2 1 36 DZ
|
|
EN 3 1 10 0 1
|
|
GN1 0 2 13 0 1
|
|
GN2 0 1 16 0 1
|
|
*
|
|
EREF 98 0 28 0 1
|
|
EP 97 0 99 0 1
|
|
EM 51 0 50 0 1
|
|
*
|
|
* VOLTAGE NOISE SOURCE
|
|
*
|
|
DN1 35 10 DEN
|
|
DN2 10 11 DEN
|
|
VN1 35 0 DC 2
|
|
VN2 0 11 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN3 12 13 DIN
|
|
DN4 13 14 DIN
|
|
VN3 12 0 DC 2
|
|
VN4 0 14 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN5 15 16 DIN
|
|
DN6 16 17 DIN
|
|
VN5 15 0 DC 2
|
|
VN6 0 17 DC 2
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT 0.439 HZ
|
|
*
|
|
R7 18 98 1.45E7
|
|
C3 18 98 25E-9
|
|
G1 98 18 5 6 5.15E-3
|
|
V2 97 19 1.5
|
|
V3 20 51 1.5
|
|
D3 18 19 DX
|
|
D4 20 18 DX
|
|
*
|
|
* POLE/ZERO PAIR AT 1.5MHz/12.7MHz
|
|
*
|
|
R8 21 98 1E3
|
|
R9 21 22 1.25E3
|
|
C4 22 98 10E-12
|
|
G2 98 21 18 28 1E-3
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R10 23 98 1
|
|
C5 23 98 62E-12
|
|
G3 98 23 21 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R11 24 98 1
|
|
C6 24 98 62E-12
|
|
G4 98 24 23 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R14 27 98 1
|
|
C8 27 98 62E-12
|
|
G5 98 27 24 28 1
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ
|
|
*
|
|
R12 25 26 1E6
|
|
C7 25 26 159.155E-12
|
|
R13 26 98 1
|
|
E2 25 98 POLY(2) 1 98 2 98 0 0.28 0.28
|
|
*
|
|
*PSRR=121dB
|
|
EPSY 98 72 POLY(1) (99,50) 0 1
|
|
RPS3 72 73 1E6
|
|
CPS3 72 73 3E-9
|
|
RPS4 73 98 1
|
|
|
|
* OUTPUT STAGE
|
|
*
|
|
R15 28 99 100E3
|
|
R16 28 50 100E3
|
|
C9 28 50 1E-6
|
|
ISY 99 50 250E-6
|
|
R17 29 99 100
|
|
R18 29 50 100
|
|
L2 29 34 1E-9
|
|
G6 32 50 27 29 10E-3
|
|
G7 33 50 29 27 10E-3
|
|
G8 29 99 99 27 10E-3
|
|
G9 50 29 27 50 10E-3
|
|
V4 30 29 1.3
|
|
V5 29 31 3.8
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
D5 27 30 DX
|
|
D6 31 27 DX
|
|
D7 99 32 DX
|
|
D8 99 33 DX
|
|
D9 50 32 DY
|
|
D10 50 33 DY
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL QX PNP(BF=5E5)
|
|
.MODEL DX D(IS=1E-12)
|
|
.MODEL DY D(IS=1E-15 BV=50)
|
|
.MODEL DZ D(IS=1E-15 BV=7.0)
|
|
.MODEL DEN D(IS=1E-12 RS=6.8E3 KF=1.95E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1)
|
|
.ENDS OP2177
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* OP284 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 3/30V, BIP, OP, Low Noise, RRIO, 2X
|
|
* Developed by: HH / ADSJ, ARG / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 4.0 (09/2009) - Increased Ccm, Cdiff
|
|
* 3.0 - Adjusted Ccm, Cdiff, and en.
|
|
* 2.0 (11/1995) - Changed input transistor betas to conform to final data sheet Ios typical spec of 60nA.
|
|
* Copyright 1993, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance with the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP284 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
Q1 5 2 3 QIN 1
|
|
Q2 6 11 3 QIN 1
|
|
Q3 7 2 4 QIP 1
|
|
Q4 8 11 4 QIP 1
|
|
DC1 2 11 DC
|
|
DC2 11 2 DC
|
|
Q5 4 9 99 QIP 1
|
|
Q6 9 9 99 QIP 1
|
|
Q7 3 10 50 QIN 1
|
|
Q8 10 10 50 QIN 1
|
|
R1 99 5 4E3
|
|
R2 99 6 4E3
|
|
R3 7 50 4E3
|
|
R4 8 50 4E3
|
|
IREF 9 10 50.5E-6
|
|
EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1
|
|
IOS 2 1 5E-9
|
|
CIN 1 2 2.3E-12
|
|
CCM1 1 50 7.2E-12
|
|
CCM2 2 50 7.2E-12
|
|
GN1 98 1 (17,98) 1E-3
|
|
GN2 98 2 (23,98) 1E-3
|
|
*
|
|
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN1 13 98 DC 2
|
|
VN2 98 15 DC 2
|
|
DN1 13 14 DEN
|
|
DN2 14 15 DEN
|
|
*
|
|
* CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN3 16 98 DC 2
|
|
VN4 98 18 DC 2
|
|
DN3 16 17 DIN
|
|
DN4 17 18 DIN
|
|
*
|
|
* 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN5 19 98 DC 2
|
|
VN6 98 24 DC 2
|
|
DN5 19 23 DIN
|
|
DN6 23 24 DIN
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
|
|
G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3
|
|
R9 20 98 1E3
|
|
*
|
|
* COMMON MODE STAGE WITH ZERO AT 100HZ
|
|
*
|
|
ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5
|
|
R10 21 22 1
|
|
R11 22 98 100E-6
|
|
C4 21 22 1.592E-3
|
|
*
|
|
* NEGATIVE ZERO AT 20MHZ
|
|
*
|
|
E1 27 98 (20,98) 1E6
|
|
R17 27 28 1
|
|
R18 28 98 1E-6
|
|
C8 25 26 7.958E-9
|
|
ENZ 25 98 (27,28) 1
|
|
VNZ 26 98 DC 0
|
|
FNZ 27 28 VNZ -1
|
|
*
|
|
* POLE AT 40MHZ
|
|
*
|
|
G4 98 29 (28,98) 1
|
|
R19 29 98 1
|
|
C9 29 98 3.979E-9
|
|
*
|
|
* POLE AT 40MHZ
|
|
*
|
|
G5 98 30 (29,98) 1
|
|
R20 30 98 1
|
|
C10 30 98 3.979E-9
|
|
*
|
|
* OUTUT STAGE
|
|
*
|
|
ISY 99 50 0.276E-3
|
|
GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6
|
|
RIN 31 50 2.75E6
|
|
VB 99 32 0.7
|
|
Q11 32 31 33 QON 1
|
|
R21 33 34 4.5E3
|
|
I1 34 50 50E-6
|
|
R22 99 35 6E3
|
|
Q12 36 36 35 QOP 1
|
|
I2 36 50 50E-6
|
|
R23 99 37 2.6E3
|
|
R24 34 38 5E3
|
|
Q13 39 36 37 QOP 1
|
|
Q14 39 38 40 QON 1.5
|
|
R25 40 50 40
|
|
Q15 39 39 41 QON 1
|
|
R26 41 42 1E3
|
|
R27 99 43 220
|
|
Q16 44 44 43 QOP 1.5
|
|
Q17 44 39 42 QON 1
|
|
R28 42 50 2E3
|
|
VSCP 99 97 DC 0
|
|
FSCP 46 99 VSCP 1
|
|
RSCP 46 99 40
|
|
Q20 44 46 99 QOP 1
|
|
Q18 45 44 97 QOP 4.5
|
|
Q19 45 34 51 QON 4.5
|
|
VSCN 51 50 DC 0
|
|
FSCN 50 47 VSCN 1
|
|
RSCN 47 50 40
|
|
Q21 34 47 50 QON 1
|
|
CC2 31 45 20E-12
|
|
CF1 31 34 15E-12
|
|
CF2 31 42 15E-12
|
|
CO1 34 45 15E-12
|
|
CO2 42 45 5E-12
|
|
D3 45 99 DX
|
|
D4 50 45 DX
|
|
.MODEL DC D(IS=130E-21)
|
|
.MODEL DX D()
|
|
.MODEL DEN D(RS=380 KF=6E-15 AF=1)
|
|
.MODEL DIN D(RS=5.358 KF=56E-15 AF=1)
|
|
.MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16)
|
|
.MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16)
|
|
.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50)
|
|
.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160)
|
|
.ENDS OP284
|
|
|
|
|
|
* OP285 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 9/30V, BIP, OP, High Slew, Low Noise, 2X
|
|
* Developed by: ARG / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (06/1992)
|
|
* Copyright 1992, 2012 by Analog Devices, Inc.
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP285 1 2 99 50 34
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE & POLE AT 100 MHZ
|
|
*
|
|
R3 5 51 2.188
|
|
R4 6 51 2.188
|
|
CIN 1 2 1.5E-12
|
|
C2 5 6 364E-12
|
|
I1 97 4 100E-3
|
|
IOS 1 2 1E-9
|
|
EOS 9 3 POLY(1) 26 28 35E-6 1
|
|
Q1 5 2 7 QX
|
|
Q2 6 9 8 QX
|
|
R5 7 4 1.672
|
|
R6 8 4 1.672
|
|
D1 2 36 DZ
|
|
D2 1 36 DZ
|
|
EN 3 1 10 0 1
|
|
GN1 0 2 13 0 1
|
|
GN2 0 1 16 0 1
|
|
*
|
|
EREF 98 0 28 0 1
|
|
EP 97 0 99 0 1
|
|
EM 51 0 50 0 1
|
|
*
|
|
* VOLTAGE NOISE SOURCE
|
|
*
|
|
DN1 35 10 DEN
|
|
DN2 10 11 DEN
|
|
VN1 35 0 DC 2
|
|
VN2 0 11 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN3 12 13 DIN
|
|
DN4 13 14 DIN
|
|
VN3 12 0 DC 2
|
|
VN4 0 14 DC 2
|
|
CN1 13 0 7.53E-3
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN5 15 16 DIN
|
|
DN6 16 17 DIN
|
|
VN5 15 0 DC 2
|
|
VN6 0 17 DC 2
|
|
CN2 16 0 7.53E-3
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT 32 HZ
|
|
*
|
|
R7 18 98 1.09E6
|
|
C3 18 98 4.55E-9
|
|
G1 98 18 5 6 4.57E-1
|
|
V2 97 19 1.4
|
|
V3 20 51 1.4
|
|
D3 18 19 DX
|
|
D4 20 18 DX
|
|
*
|
|
* POLE/ZERO PAIR AT 1.5MHz/2.7MHz
|
|
*
|
|
R8 21 98 1E3
|
|
R9 21 22 1.25E3
|
|
C4 22 98 47.2E-12
|
|
G2 98 21 18 28 1E-3
|
|
*
|
|
* POLE AT 100 MHZ
|
|
*
|
|
R10 23 98 1
|
|
C5 23 98 1.59E-9
|
|
G3 98 23 21 28 1
|
|
*
|
|
* POLE AT 100 MHZ
|
|
*
|
|
R11 24 98 1
|
|
C6 24 98 1.59E-9
|
|
G4 98 24 23 28 1
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ
|
|
*
|
|
R12 25 26 1E6
|
|
C7 25 26 159.155E-12
|
|
R13 26 98 1
|
|
E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506
|
|
*
|
|
* POLE AT 100 MHZ
|
|
*
|
|
R14 27 98 1
|
|
C8 27 98 1.59E-9
|
|
G5 98 27 24 28 1
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R15 28 99 100E3
|
|
R16 28 50 100E3
|
|
C9 28 50 1E-6
|
|
ISY 99 50 1.85E-3
|
|
R17 29 99 100
|
|
R18 29 50 100
|
|
L2 29 34 1E-9
|
|
G6 32 50 27 29 10E-3
|
|
G7 33 50 29 27 10E-3
|
|
G8 29 99 99 27 10E-3
|
|
G9 50 29 27 50 10E-3
|
|
V4 30 29 1.3
|
|
V5 29 31 3.8
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
D5 27 30 DX
|
|
D6 31 27 DX
|
|
D7 99 32 DX
|
|
D8 99 33 DX
|
|
D9 50 32 DY
|
|
D10 50 33 DY
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL QX PNP(BF=5E5)
|
|
.MODEL DX D(IS=1E-12)
|
|
.MODEL DY D(IS=1E-15 BV=50)
|
|
.MODEL DZ D(IS=1E-15 BV=7.0)
|
|
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1)
|
|
.ENDS OP285
|
|
|
|
|
|
|
|
|
|
|
|
* OP292 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 4.5/33V, BIP, OP, Low Cost, S SPLY, 2X
|
|
* Developed by: ARG / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 2.0 (03/1995)
|
|
* Copyright 1993, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP292 2 1 99 50 34
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE AND POLE AT 40MHZ
|
|
*
|
|
I1 99 4 50E-6
|
|
IOS 2 1 10E-9
|
|
EOS 2 3 POLY(1) (21,30) 1.5E-3 75
|
|
CIN 1 2 3E-12
|
|
Q1 5 1 7 QP
|
|
Q2 6 3 8 QP
|
|
R3 5 50 2E3
|
|
R4 6 50 2E3
|
|
R5 4 7 966
|
|
R6 4 8 966
|
|
C1 5 6 .995E-12
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
EREF 98 0 (30,0) 1
|
|
G1 98 9 (5,6) 500E-6
|
|
R7 9 98 210.819E3
|
|
D1 9 10 DX
|
|
D2 11 9 DX
|
|
V1 99 10 .6
|
|
V2 11 50 .6
|
|
*
|
|
* ZERO/POLE AT 6MHZ/12MHZ
|
|
*
|
|
E1 12 98 (9,30) 2
|
|
R8 12 13 1
|
|
R9 13 98 1
|
|
C3 12 13 26.526E-9
|
|
*
|
|
* ZERO AT 15MHZ
|
|
*
|
|
E2 14 98 (13,30) 1E6
|
|
R10 14 15 1E6
|
|
R11 15 98 1
|
|
C4 14 15 10.610E-15
|
|
*
|
|
* COMMON MODE STAGE WITH ZERO AT 40KHZ
|
|
*
|
|
ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5
|
|
R20 20 21 1E6
|
|
R21 21 98 1
|
|
C5 20 21 3.979E-12
|
|
*
|
|
* POLE AT 100MHZ
|
|
*
|
|
G2 98 16 (15,30) 1
|
|
R12 16 98 1
|
|
C6 16 98 1.592E-9
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
RS1 99 30 1E6
|
|
RS2 30 50 1E6
|
|
ISY 99 50 .44E-3
|
|
G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6
|
|
R16 31 50 1E6
|
|
DCL 50 31 DZ
|
|
I2 99 32 250E-6
|
|
RCL 33 50 56
|
|
M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
CC 31 32 14E-12
|
|
Q3 99 32 34 QNA
|
|
Q4 33 32 34 QPA
|
|
Q5 31 33 50 QNA
|
|
.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3
|
|
+ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4
|
|
+ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209
|
|
+ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5
|
|
+ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
|
|
.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4
|
|
+ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5
|
|
+ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4
|
|
+ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4
|
|
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
|
|
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3
|
|
+ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
|
|
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837
|
|
+ MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
|
|
.MODEL QP PNP(BF=61.5)
|
|
.MODEL DX D
|
|
.MODEL DZ D(BV=3.6)
|
|
.ENDS OP292
|
|
|
|
|
|
|
|
|
|
|
|
* OP413 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 4X
|
|
* Developed by: ARG / PMI
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (03/1994)
|
|
* Copyright 1992, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
*
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP413 3 2 7 4 6
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
R3 4 19 1.5E3
|
|
R4 4 20 1.5E3
|
|
C1 19 20 5.31E-12
|
|
I1 7 18 106E-6
|
|
IOS 2 3 25E-09
|
|
EOS 12 5 POLY(1) 51 4 25E-06 1
|
|
Q1 19 3 18 PNP1
|
|
Q2 20 12 18 PNP1
|
|
CIN 3 2 3E-12
|
|
D1 3 1 DY
|
|
D2 2 1 DY
|
|
EN 5 2 22 0 1
|
|
GN1 0 2 25 0 1E-5
|
|
GN2 0 3 28 0 1E-5
|
|
*
|
|
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
DN1 21 22 DEN
|
|
DN2 22 23 DEN
|
|
VN1 21 0 DC 2
|
|
VN2 0 23 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
DN3 24 25 DIN
|
|
DN4 25 26 DIN
|
|
VN3 24 0 DC 2
|
|
VN4 0 26 DC 2
|
|
*
|
|
* SECOND CURRENT NOISE SOURCE
|
|
*
|
|
DN5 27 28 DIN
|
|
DN6 28 29 DIN
|
|
VN5 27 0 DC 2
|
|
VN6 0 29 DC 2
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT 2HZ
|
|
*
|
|
G2 34 36 19 20 2.65E-04
|
|
R7 34 36 39E6
|
|
V3 35 4 DC 6
|
|
D4 36 35 DX
|
|
VB2 34 4 1.6
|
|
*
|
|
* SUPPLY/2 GENERATOR
|
|
*
|
|
ISY 7 4 0.2E-3
|
|
R10 7 60 40E3
|
|
R11 60 4 40E3
|
|
C3 60 0 1E-9
|
|
*
|
|
* CMRR STAGE & POLE AT 6kHZ
|
|
*
|
|
ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8
|
|
CCM 50 51 26.5E-12
|
|
RCM1 50 51 1E6
|
|
RCM2 51 4 1
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
R12 37 36 1E3
|
|
R13 38 36 500
|
|
C4 37 6 20E-12
|
|
C5 38 39 20E-12
|
|
M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
D5 39 47 DX
|
|
D6 47 45 DX
|
|
Q3 39 40 41 QPA 8
|
|
VB 7 40 DC 0.861
|
|
R14 7 41 375
|
|
Q4 41 7 43 QNA 1
|
|
R17 7 43 15
|
|
Q5 43 39 6 QNA 20
|
|
Q6 46 45 6 QPA 20
|
|
R18 46 4 15
|
|
Q7 36 46 4 QNA 1
|
|
M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9
|
|
*
|
|
* NONLINEAR MODELS USED
|
|
*
|
|
.MODEL DX D (IS=1E-15)
|
|
.MODEL DY D (IS=1E-15 BV=7)
|
|
.MODEL PNP1 PNP (BF=220)
|
|
.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1)
|
|
.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3
|
|
+ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573
|
|
+ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12
|
|
+ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
|
|
.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3
|
|
+ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13
|
|
+ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4
|
|
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
|
|
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
|
|
+ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
|
|
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4
|
|
+ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
|
|
.ENDS OP413
|
|
|
|
|
|
|
|
|
|
|
|
* OP4177 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 5/30V, BIP, OP, Low Vos, Low Ib, 4X
|
|
* Developed by: SB, ADSiV apps
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (05/2002)
|
|
* Copyright 2002, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include: Vsy=+/-15V
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP4177 1 2 99 50 34
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE & POLE AT 100 MHZ
|
|
*
|
|
R3 5 51 6.8E3
|
|
R4 6 51 6.8E3
|
|
CIN 1 2 1.5E-12
|
|
C2 5 6 3.5E-12
|
|
I1 97 4 500E-6
|
|
IOS 1 2 0.1E-9
|
|
EOS 9 3 POLY(2) (26, 28) (73, 98) 15E-6 1 1
|
|
Q1 5 2 7 QX
|
|
Q2 6 9 8 QX
|
|
R5 7 4 50
|
|
R6 8 4 50
|
|
D1 2 36 DZ
|
|
D2 1 36 DZ
|
|
EN 3 1 10 0 1
|
|
GN1 0 2 13 0 1
|
|
GN2 0 1 16 0 1
|
|
*
|
|
EREF 98 0 28 0 1
|
|
EP 97 0 99 0 1
|
|
EM 51 0 50 0 1
|
|
*
|
|
* VOLTAGE NOISE SOURCE
|
|
*
|
|
DN1 35 10 DEN
|
|
DN2 10 11 DEN
|
|
VN1 35 0 DC 2
|
|
VN2 0 11 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN3 12 13 DIN
|
|
DN4 13 14 DIN
|
|
VN3 12 0 DC 2
|
|
VN4 0 14 DC 2
|
|
*
|
|
* CURRENT NOISE SOURCE
|
|
*
|
|
DN5 15 16 DIN
|
|
DN6 16 17 DIN
|
|
VN5 15 0 DC 2
|
|
VN6 0 17 DC 2
|
|
*
|
|
* GAIN STAGE & DOMINANT POLE AT 0.439 HZ
|
|
*
|
|
R7 18 98 1.45E7
|
|
C3 18 98 25E-9
|
|
G1 98 18 5 6 5.15E-3
|
|
V2 97 19 1.5
|
|
V3 20 51 1.5
|
|
D3 18 19 DX
|
|
D4 20 18 DX
|
|
*
|
|
* POLE/ZERO PAIR AT 1.5MHz/12.7MHz
|
|
*
|
|
R8 21 98 1E3
|
|
R9 21 22 1.25E3
|
|
C4 22 98 10E-12
|
|
G2 98 21 18 28 1E-3
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R10 23 98 1
|
|
C5 23 98 62E-12
|
|
G3 98 23 21 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R11 24 98 1
|
|
C6 24 98 62E-12
|
|
G4 98 24 23 28 1
|
|
*
|
|
* POLE AT 2568 MHz
|
|
*
|
|
R14 27 98 1
|
|
C8 27 98 62E-12
|
|
G5 98 27 24 28 1
|
|
*
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ
|
|
*
|
|
R12 25 26 1E6
|
|
C7 25 26 159.155E-12
|
|
R13 26 98 1
|
|
E2 25 98 POLY(2) 1 98 2 98 0 0.28 0.28
|
|
*
|
|
*PSRR=121dB
|
|
EPSY 98 72 POLY(1) (99,50) 0 1
|
|
RPS3 72 73 1E6
|
|
CPS3 72 73 3E-9
|
|
RPS4 73 98 1
|
|
|
|
* OUTPUT STAGE
|
|
*
|
|
R15 28 99 100E3
|
|
R16 28 50 100E3
|
|
C9 28 50 1E-6
|
|
ISY 99 50 250E-6
|
|
R17 29 99 100
|
|
R18 29 50 100
|
|
L2 29 34 1E-9
|
|
G6 32 50 27 29 10E-3
|
|
G7 33 50 29 27 10E-3
|
|
G8 29 99 99 27 10E-3
|
|
G9 50 29 27 50 10E-3
|
|
V4 30 29 1.3
|
|
V5 29 31 3.8
|
|
F1 29 0 V4 1
|
|
F2 0 29 V5 1
|
|
D5 27 30 DX
|
|
D6 31 27 DX
|
|
D7 99 32 DX
|
|
D8 99 33 DX
|
|
D9 50 32 DY
|
|
D10 50 33 DY
|
|
*
|
|
* MODELS USED
|
|
*
|
|
.MODEL QX PNP(BF=5E5)
|
|
.MODEL DX D(IS=1E-12)
|
|
.MODEL DY D(IS=1E-15 BV=50)
|
|
.MODEL DZ D(IS=1E-15 BV=7.0)
|
|
.MODEL DEN D(IS=1E-12 RS=6.8E3 KF=1.95E-15 AF=1)
|
|
.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1)
|
|
.ENDS OP4177
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* OP484 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 3/30V, BIP, OP, Low Noise, RRIO, 4X
|
|
* Developed by: ARG / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (11/1995)
|
|
* Copyright 1993, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP484 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
Q1 5 2 3 QIN 1
|
|
Q2 6 11 3 QIN 1
|
|
Q3 7 2 4 QIP 1
|
|
Q4 8 11 4 QIP 1
|
|
DC1 2 11 DC
|
|
DC2 11 2 DC
|
|
Q5 4 9 99 QIP 1
|
|
Q6 9 9 99 QIP 1
|
|
Q7 3 10 50 QIN 1
|
|
Q8 10 10 50 QIN 1
|
|
R1 99 5 4E3
|
|
R2 99 6 4E3
|
|
R3 7 50 4E3
|
|
R4 8 50 4E3
|
|
IREF 9 10 50.5E-6
|
|
EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1
|
|
IOS 2 1 1E-9
|
|
CIN 1 2 2E-12
|
|
GN1 98 1 (17,98) 1E-3
|
|
GN2 98 2 (23,98) 1E-3
|
|
*
|
|
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN1 13 98 DC 2
|
|
VN2 98 15 DC 2
|
|
DN1 13 14 DEN
|
|
DN2 14 15 DEN
|
|
*
|
|
* CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN3 16 98 DC 2
|
|
VN4 98 18 DC 2
|
|
DN3 16 17 DIN
|
|
DN4 17 18 DIN
|
|
*
|
|
* 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE
|
|
*
|
|
VN5 19 98 DC 2
|
|
VN6 98 24 DC 2
|
|
DN5 19 23 DIN
|
|
DN6 23 24 DIN
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
|
|
G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3
|
|
R9 20 98 1E3
|
|
*
|
|
* COMMON MODE STAGE WITH ZERO AT 100HZ
|
|
*
|
|
ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5
|
|
R10 21 22 1
|
|
R11 22 98 100E-6
|
|
C4 21 22 1.592E-3
|
|
*
|
|
* NEGATIVE ZERO AT 20MHZ
|
|
*
|
|
E1 27 98 (20,98) 1E6
|
|
R17 27 28 1
|
|
R18 28 98 1E-6
|
|
C8 25 26 7.958E-9
|
|
ENZ 25 98 (27,28) 1
|
|
VNZ 26 98 DC 0
|
|
FNZ 27 28 VNZ -1
|
|
*
|
|
* POLE AT 40MHZ
|
|
*
|
|
G4 98 29 (28,98) 1
|
|
R19 29 98 1
|
|
C9 29 98 3.979E-9
|
|
*
|
|
* POLE AT 40MHZ
|
|
*
|
|
G5 98 30 (29,98) 1
|
|
R20 30 98 1
|
|
C10 30 98 3.979E-9
|
|
*
|
|
* OUTUT STAGE
|
|
*
|
|
ISY 99 50 0.276E-3
|
|
GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6
|
|
RIN 31 50 2.75E6
|
|
VB 99 32 0.7
|
|
Q11 32 31 33 QON 1
|
|
R21 33 34 4.5E3
|
|
I1 34 50 50E-6
|
|
R22 99 35 6E3
|
|
Q12 36 36 35 QOP 1
|
|
I2 36 50 50E-6
|
|
R23 99 37 2.6E3
|
|
R24 34 38 5E3
|
|
Q13 39 36 37 QOP 1
|
|
Q14 39 38 40 QON 1.5
|
|
R25 40 50 40
|
|
Q15 39 39 41 QON 1
|
|
R26 41 42 1E3
|
|
R27 99 43 220
|
|
Q16 44 44 43 QOP 1.5
|
|
Q17 44 39 42 QON 1
|
|
R28 42 50 2E3
|
|
VSCP 99 97 DC 0.088
|
|
FSCP 46 99 VSCP 1
|
|
RSCP 46 99 40
|
|
Q20 44 46 99 QOP 1
|
|
Q18 45 44 97 QOP 4.5
|
|
Q19 45 34 51 QON 4.5
|
|
VSCN 51 50 DC 0.081
|
|
FSCN 50 47 VSCN 1
|
|
RSCN 47 50 40
|
|
Q21 34 47 50 QON 1
|
|
CC2 31 45 20E-12
|
|
CF1 31 34 15E-12
|
|
CF2 31 42 15E-12
|
|
CO1 34 45 15E-12
|
|
CO2 42 45 5E-12
|
|
D3 45 99 DX
|
|
D4 50 45 DX
|
|
.MODEL DC D(IS=130E-21)
|
|
.MODEL DX D()
|
|
.MODEL DEN D(RS=100 KF=12E-15 AF=1)
|
|
.MODEL DIN D(RS=5.358 KF=56E-15 AF=1)
|
|
.MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16)
|
|
.MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16)
|
|
.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50)
|
|
.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160)
|
|
.ENDS OP484
|
|
|
|
|
|
|
|
|
|
|
|
* OP492 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: 4.5/33V, BIP, OP, Low Cost, S SPLY, 4X
|
|
* Developed by: ARG / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 2.0 (03/1995)
|
|
* Copyright 1993, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT OP492 2 1 99 50 34
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* INPUT STAGE AND POLE AT 40MHZ
|
|
*
|
|
I1 99 4 50E-6
|
|
IOS 2 1 10E-9
|
|
EOS 2 3 POLY(1) (21,30) 1.5E-3 75
|
|
CIN 1 2 3E-12
|
|
Q1 5 1 7 QP
|
|
Q2 6 3 8 QP
|
|
R3 5 50 2E3
|
|
R4 6 50 2E3
|
|
R5 4 7 966
|
|
R6 4 8 966
|
|
C1 5 6 .995E-12
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
EREF 98 0 (30,0) 1
|
|
G1 98 9 (5,6) 500E-6
|
|
R7 9 98 210.819E3
|
|
D1 9 10 DX
|
|
D2 11 9 DX
|
|
V1 99 10 .6
|
|
V2 11 50 .6
|
|
*
|
|
* ZERO/POLE AT 6MHZ/12MHZ
|
|
*
|
|
E1 12 98 (9,30) 2
|
|
R8 12 13 1
|
|
R9 13 98 1
|
|
C3 12 13 26.526E-9
|
|
*
|
|
* ZERO AT 15MHZ
|
|
*
|
|
E2 14 98 (13,30) 1E6
|
|
R10 14 15 1E6
|
|
R11 15 98 1
|
|
C4 14 15 10.610E-15
|
|
*
|
|
* COMMON MODE STAGE WITH ZERO AT 40KHZ
|
|
*
|
|
ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5
|
|
R20 20 21 1E6
|
|
R21 21 98 1
|
|
C5 20 21 3.979E-12
|
|
*
|
|
* POLE AT 100MHZ
|
|
*
|
|
G2 98 16 (15,30) 1
|
|
R12 16 98 1
|
|
C6 16 98 1.592E-9
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
RS1 99 30 1E6
|
|
RS2 30 50 1E6
|
|
ISY 99 50 .44E-3
|
|
G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6
|
|
R16 31 50 1E6
|
|
DCL 50 31 DZ
|
|
I2 99 32 250E-6
|
|
RCL 33 50 56
|
|
M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
|
|
CC 31 32 14E-12
|
|
Q3 99 32 34 QNA
|
|
Q4 33 32 34 QPA
|
|
Q5 31 33 50 QNA
|
|
.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3
|
|
+ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4
|
|
+ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209
|
|
+ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5
|
|
+ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
|
|
.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4
|
|
+ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5
|
|
+ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4
|
|
+ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4
|
|
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
|
|
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3
|
|
+ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
|
|
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837
|
|
+ MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
|
|
.MODEL QP PNP(BF=61.5)
|
|
.MODEL DX D
|
|
.MODEL DZ D(BV=3.6)
|
|
.ENDS OP492
|
|
|
|
|
|
|
|
|
|
|
|
* OP727 SPICE Macro-model Typical Values
|
|
* Description: Amplifier
|
|
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 2X
|
|
* Developed by: RM / ADSC, HH / ADSJ
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.2 (04/2009) - Corrected EVP, EVN
|
|
* 1.1 (08/2000)
|
|
* Copyright 2000, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP727 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* PNP INPUT STAGE
|
|
*
|
|
Q1 5 7 3 PIX
|
|
Q2 6 2 3 PIX
|
|
RC1 5 50 8000
|
|
RC2 6 50 8000
|
|
C1 5 6 0.5E-12
|
|
D1 3 8 DX
|
|
V1 99 8 DC 1.0
|
|
I1 99 3 50E-6
|
|
EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
|
|
IOS 2 1 1E-9
|
|
*
|
|
* PSRR=120dB, ZERO AT 150Hz
|
|
*
|
|
RPS1 70 0 1E+6
|
|
RPS2 71 0 1E+6
|
|
CPS1 99 70 1E-5
|
|
CPS2 50 71 1E-5
|
|
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
|
|
RPS3 72 73 1E+6
|
|
CPS3 72 73 1.06E-9
|
|
RPS4 73 98 1
|
|
*
|
|
EVP 97 98 (99,50) 0.5
|
|
EVN 51 98 (50,99) 0.5
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 16.45E-3
|
|
HN 81 98 VN1 15
|
|
RN2 81 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
GSY 99 50 POLY(1) (99,50) 0 2.6E-6
|
|
*
|
|
*
|
|
* CMRR 110dB, ZERO AT 400Hz
|
|
*
|
|
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
|
|
RCM1 21 22 1E+6
|
|
CCM1 21 22 0.397E-9
|
|
RCM2 22 98 1
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 POLY(1) (5,6) 0 28.8E-6
|
|
R1 30 98 2.02E+8
|
|
CF 45 30 50E-12
|
|
D3 30 97 DX
|
|
D4 51 30 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 45 46 99 99 POX L=1E-6 W=0.329E-3
|
|
M6 45 47 50 50 NOX L=1E-6 W=0.496E-3
|
|
EG1 99 46 POLY(1) (98,30) 0.6299 1
|
|
EG2 47 50 POLY(1) (30,98) 0.5739 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
|
|
.MODEL DX D(IS=1E-14,RS=5)
|
|
.ENDS OP727
|
|
|
|
|
|
|
|
|
|
|
|
* OP747 SPICE Macro-model Typical Values
|
|
* Description: Amplifier
|
|
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 4X
|
|
* Developed by: RM / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.2 (04/2009) - Corrected EVP, EVN
|
|
* 1.1 (08/2000)
|
|
* Copyright 2000, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP747 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* PNP INPUT STAGE
|
|
*
|
|
Q1 5 7 3 PIX
|
|
Q2 6 2 3 PIX
|
|
RC1 5 50 8000
|
|
RC2 6 50 8000
|
|
C1 5 6 0.5E-12
|
|
D1 3 8 DX
|
|
V1 99 8 DC 1.0
|
|
I1 99 3 50E-6
|
|
EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
|
|
IOS 2 1 1E-9
|
|
*
|
|
* PSRR=120dB, ZERO AT 150Hz
|
|
*
|
|
RPS1 70 0 1E+6
|
|
RPS2 71 0 1E+6
|
|
CPS1 99 70 1E-5
|
|
CPS2 50 71 1E-5
|
|
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
|
|
RPS3 72 73 1E+6
|
|
CPS3 72 73 1.06E-9
|
|
RPS4 73 98 1
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 16.45E-3
|
|
HN 81 98 VN1 15
|
|
RN2 81 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
GSY 99 50 POLY(1) (99,50) 0 2.6E-6
|
|
EVP 97 98 POLY(1) (99,50) 0 0.5
|
|
EVN 51 98 POLY(1) (50,99) 0 0.5
|
|
*
|
|
*
|
|
* CMRR 110dB, ZERO AT 400Hz
|
|
*
|
|
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
|
|
RCM1 21 22 1E+6
|
|
CCM1 21 22 0.397E-9
|
|
RCM2 22 98 1
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 POLY(1) (5,6) 0 28.8E-6
|
|
R1 30 98 2.02E+8
|
|
CF 45 30 50E-12
|
|
D3 30 97 DX
|
|
D4 51 30 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 45 46 99 99 POX L=1E-6 W=0.329E-3
|
|
M6 45 47 50 50 NOX L=1E-6 W=0.496E-3
|
|
EG1 99 46 POLY(1) (98,30) 0.6299 1
|
|
EG2 47 50 POLY(1) (30,98) 0.5739 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
|
|
.MODEL DX D(IS=1E-14,RS=5)
|
|
.ENDS OP747
|
|
|
|
|
|
|
|
|
|
|
|
* OP777 SPICE Macro-model Typical Values
|
|
* Description: Amplifier
|
|
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 1X
|
|
* Developed by: RM / ADSC
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.2 (04/2009) - Corrected EVP, EVN
|
|
* 1.1 (08/2000)
|
|
* Copyright 2000, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
|
* indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes:
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT OP777 1 2 99 50 45
|
|
*#ASSOC Category="Op-amps" symbol=opamp
|
|
*
|
|
* PNP INPUT STAGE
|
|
*
|
|
Q1 5 7 3 PIX
|
|
Q2 6 2 3 PIX
|
|
RC1 5 50 8000
|
|
RC2 6 50 8000
|
|
C1 5 6 0.5E-12
|
|
D1 3 8 DX
|
|
V1 99 8 DC 1.0
|
|
I1 99 3 50E-6
|
|
EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
|
|
IOS 2 1 1E-9
|
|
*
|
|
* PSRR=120dB, ZERO AT 150Hz
|
|
*
|
|
RPS1 70 0 1E+6
|
|
RPS2 71 0 1E+6
|
|
CPS1 99 70 1E-5
|
|
CPS2 50 71 1E-5
|
|
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
|
|
RPS3 72 73 1E+6
|
|
CPS3 72 73 1.06E-9
|
|
RPS4 73 98 1
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 16.45E-3
|
|
HN 81 98 VN1 15
|
|
RN2 81 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
GSY 99 50 POLY(1) (99,50) 0 2.6E-6
|
|
EVP 97 98 (99,50) 0.5
|
|
EVN 51 98 (50,99) 0.5
|
|
*
|
|
*
|
|
* CMRR 110dB, ZERO AT 400Hz
|
|
*
|
|
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
|
|
RCM1 21 22 1E+6
|
|
CCM1 21 22 0.397E-9
|
|
RCM2 22 98 1
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 POLY(1) (5,6) 0 28.8E-6
|
|
R1 30 98 2.02E+8
|
|
CF 45 30 50E-12
|
|
D3 30 97 DX
|
|
D4 51 30 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 45 46 99 99 POX L=1E-6 W=0.329E-3
|
|
M6 45 47 50 50 NOX L=1E-6 W=0.496E-3
|
|
EG1 99 46 POLY(1) (98,30) 0.6299 1
|
|
EG2 47 50 POLY(1) (30,98) 0.5739 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
|
|
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
|
|
.MODEL DX D(IS=1E-14,RS=5)
|
|
.ENDS OP777
|
|
|
|
* AD8235 SPICE Macro-model
|
|
* Description: Amplifier
|
|
* Generic Desc: CMOS, InAmp, 40 microA, WLCSP
|
|
* Developed by:
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 1.0 (12/2009)
|
|
* Copyright 2009, 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this
|
|
* model indicates your acceptance of the terms and provisions in the License Statement.
|
|
*
|
|
* BEGIN Notes: VSY=5V, T=25�C
|
|
*
|
|
* Not Modeled:
|
|
*
|
|
* Parameters modeled include:
|
|
*
|
|
* END Notes
|
|
*
|
|
* Node Assignments
|
|
* -input
|
|
* | rg1
|
|
* | | rg2
|
|
* | | | +input
|
|
* | | | | shutdwn Neg Supply
|
|
* | | | | | | ref
|
|
* | | | | | | | out
|
|
* | | | | | | | | Pos Supply
|
|
* | | | | | | | | |
|
|
.SUBCKT AD8235 Vin- RG- RG+ Vin+ SDN VNEG REF VOUT VPOS
|
|
*Amplifiers
|
|
X_U1 Vin- RG- 1 2 9 AMPA
|
|
X_U2 Vin+ 7 1 2 VOUT AMPB
|
|
*Gain Error for RG resistor
|
|
R5 7 RG+ 6
|
|
*Adjustable Supply Current for Low Supply Voltage
|
|
I3 1 2 6.5E-6
|
|
G1 1 2 2 1 1.5E-6
|
|
* Shutdown Switches
|
|
S1 1 VPOS SDN VNEG SW
|
|
S2 2 VNEG SDN VNEG SW
|
|
*Resistor Network
|
|
R1 REF RG- 209.8K
|
|
R2 RG- 9 52.5K
|
|
R3 9 7 52.5K
|
|
R4 7 VOUT 209.85K
|
|
*Switch Model
|
|
.MODEL SW VSWITCH(VON=1.3 VOFF=0.5 RON=1 ROFF=1E9)
|
|
.ENDS AD8235
|
|
*$
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT AMPA 1 2 99 50 45
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
M1 4 7 8 8 PIX L=2E-6 W=9.070E-04
|
|
M2 6 2 8 8 PIX L=2E-6 W=9.070E-04
|
|
Cinp 1 50 4.2pF
|
|
Cinn 2 50 4.2pF
|
|
Cdiff 1 2 3pF
|
|
RD1 4 50 5.333E+04
|
|
RD2 6 50 5.333E+04
|
|
C1 4 6 7.650E-12
|
|
I1 99 8 7.500E-06
|
|
V1 9 8 +0.025E-00
|
|
D1 9 99 DX
|
|
EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 0 1 1 1 1
|
|
IOS 1 2 -5.0E-12
|
|
*
|
|
* CMRR=95dB, POLE AT 3500 Hz
|
|
*
|
|
E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02
|
|
R10 72 73 4.613E+01
|
|
R20 73 98 3.183E-02
|
|
C10 72 73 1.000E-06
|
|
*
|
|
* PSRR=100dB, POLE AT 100 Hz
|
|
*
|
|
EPSY 21 98 POLY(1) (99,50) -0.181E-00 -0.03E-00
|
|
RPS1 21 22 1.274E+04
|
|
RPS2 22 98 2.989E-00
|
|
CPS1 21 22 0.20E-07
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 17.500E-3
|
|
HN 81 98 VN1 4.62E+1
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER = 20000 Hz
|
|
*
|
|
DFN 82 98 DNOISE
|
|
VFN 82 98 DC 0.6531
|
|
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
|
|
RFN 83 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
|
|
GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06
|
|
EVP 97 98 (99,50) 0.5
|
|
EVN 51 98 (50,99) 0.5
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 (4,6) 4.474E-04
|
|
R1 30 98 1.00E+06
|
|
CF 30 31 1.55E-08
|
|
RZ 455 31 1.2280E-03
|
|
EZ 455 98 (451 98) 1
|
|
V3 32 30 0.279E+00
|
|
V4 30 33 0.362E-00
|
|
D3 32 97 DX
|
|
D4 51 33 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 451 46 99 99 POX L=1E-6 W=3.940E-04
|
|
M6 451 47 50 50 NOX L=1E-6 W=4.598E-04
|
|
Lout 451 45 10pH
|
|
EG1 99 46 POLY(1) (98,30) 3.598E-01 1
|
|
EG2 47 50 POLY(1) (30,98) 3.574E-01 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0)
|
|
.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
|
|
.MODEL DX D(IS=1E-14,RS=0.1)
|
|
.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11)
|
|
*
|
|
*
|
|
.ENDS AMPA
|
|
*
|
|
*$
|
|
* Node Assignments
|
|
* noninverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
* | | | | |
|
|
.SUBCKT AMPB 1 2 99 50 45
|
|
*
|
|
* INPUT STAGE
|
|
*
|
|
M1 4 7 8 8 PIX L=2E-6 W=9.070E-04
|
|
M2 6 2 8 8 PIX L=2E-6 W=9.070E-04
|
|
Cinp 1 50 4.2pF
|
|
Cinn 2 50 4.2pF
|
|
Cdiff 1 2 3pF
|
|
RD1 4 50 5.333E+04
|
|
RD2 6 50 5.333E+04
|
|
C1 4 6 7.650E-12
|
|
I1 99 8 7.500E-06
|
|
V1 9 8 +0.025E-00
|
|
D1 9 99 DX
|
|
EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 0.926m 1 1 1 1
|
|
IOS 1 2 -10E-12
|
|
*
|
|
* CMRR=95dB, POLE AT 3500 Hz
|
|
*
|
|
E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02
|
|
R10 72 73 4.613E+01
|
|
R20 73 98 3.183E-02
|
|
C10 72 73 1.000E-06
|
|
*
|
|
* PSRR=100dB, POLE AT 100 Hz
|
|
*
|
|
EPSY 21 98 POLY(1) (99,50) -0.181E-00 0.03E-00
|
|
RPS1 21 22 2.274E+04
|
|
RPS2 22 98 1.989E-00
|
|
CPS1 21 22 0.20E-07
|
|
*
|
|
* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz)
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 17.500E-3
|
|
HN 81 98 VN1 4.62E+1
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER = 20000 Hz
|
|
*
|
|
DFN 82 98 DNOISE
|
|
VFN 82 98 DC 0.6531
|
|
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
|
|
RFN 83 98 1
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
|
|
GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06
|
|
EVP 97 98 (99,50) 0.5
|
|
EVN 51 98 (50,99) 0.5
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G1 98 30 (4,6) 4.474E-04
|
|
R1 30 98 1.00E+06
|
|
CF 30 31 1.55E-08
|
|
RZ 455 31 1.2280E-03
|
|
EZ 455 98 (451 98) 1
|
|
V3 32 30 0.279E+00
|
|
V4 30 33 0.362E-00
|
|
D3 32 97 DX
|
|
D4 51 33 DX
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
M5 451 46 99 99 POX L=1E-6 W=3.940E-04
|
|
M6 451 47 50 50 NOX L=1E-6 W=4.598E-04
|
|
Lout 451 45 10pH
|
|
EG1 99 46 POLY(1) (98,30) 3.598E-01 1
|
|
EG2 47 50 POLY(1) (30,98) 3.574E-01 1
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0)
|
|
.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0)
|
|
.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
|
|
.MODEL DX D(IS=1E-14,RS=0.1)
|
|
.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11)
|
|
*
|
|
*
|
|
.ENDS AMPB
|
|
*
|
|
*$
|
|
* AD8236 SPICE Macro-model
|
|
* Description: Instrumentation, Amplifier
|
|
* Generic Desc: CMOS, InAmp, 40 microA, MSOP
|
|
* Developed by: GC, KF
|
|
* Revision History: 08/10/2012 - Updated to new header style
|
|
* 09/18/2015 - Updated model to latest coding standards
|
|
* 2.0 (beta3) (01/2016)
|
|
* Copyright 2009, 2015 by Analog Devices
|
|
*
|
|
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
|
|
*for License Statement. Use of this model indicates your acceptance
|
|
*of the terms and provisions in the License Staement.
|
|
*
|
|
* BEGIN Notes: VSY=5V, T=25�C
|
|
**Not modeled: Distortion, PSRR, Overload Recovery,
|
|
* Shutdown Turn On/Turn Off time
|
|
*
|
|
*Parameters modeled include:
|
|
* Vos, Ibias, Supply Current, Input CM limits and Typ output voltge swing over full supply range,
|
|
* Bandwidth over all gains, Slew Rate, Output current limits, Voltage & Current Noise,
|
|
* Capacitive load drive, CMRR, Output Swing vs. Load Resistance
|
|
* Single supply & offset supply functionality.
|
|
* END Notes
|
|
*
|
|
*
|
|
* Node Assignments
|
|
* -input
|
|
* | rg1
|
|
* | | rg2
|
|
* | | | +input
|
|
* | | | |
|
|
* | | | | Neg Supply
|
|
* | | | | | ref out
|
|
* | | | | | | | Pos Supply
|
|
* | | | | | | | |
|
|
*
|
|
.SUBCKT AD8236 Vin- RG- RG+ Vin+ VNEG REF VOUT VPOS
|
|
*
|
|
*Amplifiers
|
|
X_U1 Vin- RG- VPOSa VNEGa 9 AMPA
|
|
X_U2 Vin+ 7 VPOSa VNEGa VOUT AMPB
|
|
*
|
|
*Charge pump for VPOS and VNEG
|
|
VposCP VPOSa VPOS dc 0.58
|
|
VnegCP VNEG VNEGa dc 0.57
|
|
*
|
|
*Gain Error for RG resistor
|
|
R5 7 RG+ 6
|
|
*
|
|
*Adjustable Supply Current for Low Supply Voltage
|
|
*I3 VPOS VNEG 6.5E-6
|
|
*G1 VPOS VNEG VNEG VPOS 1.5E-6
|
|
*
|
|
*Resistor Network
|
|
R1 REF RG- 209.8K
|
|
R2 RG- 9 52.5K
|
|
R3 9 7 52.5K
|
|
R4 7 VOUT 209.85K
|
|
.Subckt AMPA 100 101 102 103 104
|
|
*
|
|
***Power Supplies***
|
|
Rz1 102 1020 1e-6
|
|
Rz2 103 1030 1e-6
|
|
Ibias 1020 1030 dc 0.001e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 0.015e-3
|
|
RSW1 98 1030 1e-3
|
|
R1 1020 99 1e7
|
|
R2 99 1030 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
RSW2 1 100 1e-3
|
|
RSW3 9 101 1e-3
|
|
VOS 1 2 dc -500e-6
|
|
IbiasP 110 2 dc 1.5e-12
|
|
IbiasN 110 9 dc 1.5e-12
|
|
RinCMP 110 2 110000e6
|
|
RinCMN 9 110 110000e6
|
|
CinCMP 110 2 4.2e-12
|
|
CinCMN 9 110 4.2e-12
|
|
IOS 9 2 0.0000005e-6
|
|
RinDiff 9 2 220000e3
|
|
CinDiff 9 2 3e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 1e3
|
|
RX1 40 3 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 0.46
|
|
VinN 42 112 dc 0.46
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.4071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.4071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.4071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.4071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 1e12
|
|
RcmrrN 10 9 1e12
|
|
g10 11 110 10 110 -1e-10
|
|
Lcmrr 11 12 1e-12
|
|
Rcmrr 12 110 1e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 104 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 0.1 Hz***
|
|
g210 210 110 200 110 0.0025e-6
|
|
R210 210 110 1591547.63e6
|
|
C210 210 110 1e-12
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 5.022
|
|
VoutN 64 66 dc 5.022
|
|
e60 65 110 111 110 1.01
|
|
e61 66 110 112 110 1.01
|
|
*
|
|
*
|
|
***Pole at 1000000Hz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 1000
|
|
C220 220 110 159.1548e-12
|
|
*
|
|
***Pole at 0.4MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 1000
|
|
C230 230 110 397.8869e-12
|
|
*
|
|
***Pole at 0.5MHz***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 1000
|
|
C240 240 110 318.3095e-12
|
|
*
|
|
***Buffer***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 1000
|
|
*
|
|
***Buffer***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 1000
|
|
*
|
|
***Buffer***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 1000
|
|
*
|
|
***Buffer***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 1000
|
|
*
|
|
***Buffer***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 1000
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 1000
|
|
*
|
|
***Buffer***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 10
|
|
*
|
|
***Buffer***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 10
|
|
e295 295 110 292 110 1
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 180
|
|
Lout 303 310 10e-9
|
|
Cout 310 110 2e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc 3.836
|
|
VIoutN 304 306 dc 3.836
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 1.27
|
|
VoutN1 74 112 dc 1.26
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc 102 314 diode
|
|
RX5 311 312 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 103 diode
|
|
*
|
|
*
|
|
RSW4 104 313 1e-3
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model DClamp D(IS=1E-15 IBV=1E-13 VJ=0.1)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=10.821)
|
|
.model DzSlewN D(BV=2.842)
|
|
.model DVnoisy D(IS=7.49e-14 KF=9.87e-18)
|
|
.model DINnoisy D(IS=8.58e-21 KF=0.00e0)
|
|
.model DIPnoisy D(IS=8.58e-21 KF=0.00e0)
|
|
*
|
|
*
|
|
.ENDS AMPA
|
|
*
|
|
.subckt AMPB 100 101 102 103 104
|
|
*
|
|
***Power Supplies***
|
|
Rz1 102 1020 1e-6
|
|
Rz2 103 1030 1e-6
|
|
Ibias 1020 1030 dc 0.001e-3
|
|
DzPS 98 1020 diode
|
|
Iquies 1020 98 dc 0.015e-3
|
|
RSW1 98 1030 1e-3
|
|
R1 1020 99 1e7
|
|
R2 99 1030 1e7
|
|
e1 111 110 1020 110 1
|
|
e2 110 112 110 1030 1
|
|
e3 110 0 99 0 1
|
|
*
|
|
*
|
|
***Inputs***
|
|
RSW2 1 100 1e-3
|
|
RSW3 9 101 1e-3
|
|
VOS 1 2 dc 500e-6
|
|
IbiasP 110 2 dc 0.000001e-6
|
|
IbiasN 110 9 dc 0.000001e-6
|
|
RinCMP 110 2 110000e6
|
|
RinCMN 9 110 110000e6
|
|
CinCMP 110 2 4.2e-12
|
|
CinCMN 9 110 4.2e-12
|
|
IOS 9 2 0.0000005e-6
|
|
RinDiff 9 2 220000e3
|
|
CinDiff 9 2 3e-12
|
|
*
|
|
*
|
|
***Non-Inverting Input with Clamp***
|
|
g1 3 110 110 2 0.001
|
|
RInP 3 110 1e3
|
|
RX1 40 3 0.001
|
|
DInP 40 41 diode
|
|
DInN 42 40 diode
|
|
VinP 111 41 dc 0.46
|
|
VinN 42 112 dc 0.46
|
|
*
|
|
*
|
|
***Vnoise***
|
|
hVn 6 5 Vmeas1 707.10678
|
|
Vmeas1 20 110 DC 0
|
|
Vvn 21 110 dc 0.65
|
|
Dvn 21 20 DVnoisy
|
|
hVn1 6 7 Vmeas2 707.10678
|
|
Vmeas2 22 110 dc 0
|
|
Vvn1 23 110 dc 0.65
|
|
Dvn1 23 22 DVnoisy
|
|
*
|
|
*
|
|
***Inoise***
|
|
FnIN 9 110 Vmeas3 0.4071068
|
|
Vmeas3 51 110 dc 0
|
|
VnIN 50 110 dc 0.65
|
|
DnIN 50 51 DINnoisy
|
|
FnIN1 110 9 Vmeas4 0.4071068
|
|
Vmeas4 53 110 dc 0
|
|
VnIN1 52 110 dc 0.65
|
|
DnIN1 52 53 DINnoisy
|
|
*
|
|
FnIP 2 110 Vmeas5 0.4071068
|
|
Vmeas5 31 110 dc 0
|
|
VnIP 30 110 dc 0.65
|
|
DnIP 30 31 DIPnoisy
|
|
FnIP1 110 2 Vmeas6 0.4071068
|
|
Vmeas6 33 110 dc 0
|
|
VnIP1 32 110 dc 0.65
|
|
DnIP1 32 33 DIPnoisy
|
|
*
|
|
*
|
|
***CMRR***
|
|
RcmrrP 3 10 1e12
|
|
RcmrrN 10 9 1e12
|
|
g10 11 110 10 110 -1e-10
|
|
Lcmrr 11 12 1e-12
|
|
Rcmrr 12 110 1e3
|
|
e4 5 3 11 110 1
|
|
*
|
|
*
|
|
**
|
|
*
|
|
***Feedback Pin***
|
|
*RF 105 104 0.001
|
|
*
|
|
*
|
|
***VFB Stage***
|
|
g200 200 110 7 9 1
|
|
R200 200 110 250
|
|
DzSlewP 201 200 DzSlewP
|
|
DzSlewN 201 110 DzSlewN
|
|
*
|
|
*
|
|
***Dominant Pole at 0.1 Hz***
|
|
g210 210 110 200 110 0.0025e-6
|
|
R210 210 110 1591547.63e6
|
|
C210 210 110 1e-12
|
|
*
|
|
*
|
|
***Output Voltage Clamp-1***
|
|
RX2 60 210 0.001
|
|
DzVoutP 61 60 DzVoutP
|
|
DzVoutN 60 62 DzVoutN
|
|
DVoutP 61 63 diode
|
|
DVoutN 64 62 diode
|
|
VoutP 65 63 dc 5.022
|
|
VoutN 64 66 dc 5.022
|
|
e60 65 110 111 110 1.01
|
|
e61 66 110 112 110 1.01
|
|
*
|
|
*
|
|
***Pole at 1000000Hz***
|
|
g220 220 110 210 110 0.001
|
|
R220 220 110 1000
|
|
C220 220 110 159.1548e-12
|
|
*
|
|
***Pole at 0.4MHz***
|
|
g230 230 110 220 110 0.001
|
|
R230 230 110 1000
|
|
C230 230 110 397.8869e-12
|
|
*
|
|
***Pole at 0.5MHz***
|
|
g240 240 110 230 110 0.001
|
|
R240 240 110 1000
|
|
C240 240 110 318.3095e-12
|
|
*
|
|
***Buffer***
|
|
g245 245 110 240 110 0.001
|
|
R245 245 110 1000
|
|
*
|
|
***Buffer***
|
|
g250 250 110 245 110 0.001
|
|
R250 250 110 1000
|
|
*
|
|
***Buffer***
|
|
g255 255 110 250 110 0.001
|
|
R255 255 110 1000
|
|
*
|
|
***Buffer***
|
|
g260 260 110 255 110 0.001
|
|
R260 260 110 1000
|
|
*
|
|
***Buffer***
|
|
g265 265 110 260 110 0.001
|
|
R265 265 110 1000
|
|
*
|
|
***Buffer***
|
|
g270 270 110 265 110 0.001
|
|
R270 270 110 1000
|
|
*
|
|
***Buffer***
|
|
e280 280 110 270 110 1
|
|
R280 280 285 10
|
|
*
|
|
***Buffer***
|
|
e290 290 110 285 110 1
|
|
R290 290 292 10
|
|
e295 295 110 292 110 1
|
|
*
|
|
*
|
|
***Output Stage***
|
|
g300 300 110 295 110 0.001
|
|
R300 300 110 1000
|
|
e301 301 110 300 110 1
|
|
Rout 302 303 180
|
|
Lout 303 310 1e-9
|
|
Cout 310 110 2e-12
|
|
*
|
|
*
|
|
***Output Current Limit***
|
|
H1 301 304 Vsense1 100
|
|
Vsense1 301 302 dc 0
|
|
VIoutP 305 304 dc 3.836
|
|
VIoutN 304 306 dc 3.836
|
|
DIoutP 307 305 diode
|
|
DIoutN 306 307 diode
|
|
Rx3 307 300 0.001
|
|
*
|
|
*
|
|
***Output Clamp-2***
|
|
VoutP1 111 73 dc 1.27
|
|
VoutN1 74 112 dc 1.26
|
|
DVoutP1 75 73 diode
|
|
DVoutN1 74 75 diode
|
|
RX4 75 310 0.001
|
|
*
|
|
*
|
|
***Supply Currents***
|
|
FIoVcc 314 110 Vmeas8 1
|
|
Vmeas8 310 311 dc 0
|
|
R314 110 314 1e9
|
|
DzOVcc 110 314 diode
|
|
DOVcc 102 314 diode
|
|
RX5 311 312 0.001
|
|
FIoVee 315 110 Vmeas9 1
|
|
Vmeas9 312 313 dc 0
|
|
R315 315 110 1e9
|
|
DzOVee 315 110 diode
|
|
DOVee 315 103 diode
|
|
*
|
|
*
|
|
RSW4 104 313 1e-3
|
|
*
|
|
*
|
|
*** Common Models ***
|
|
.model diode d(bv=100)
|
|
.model DClamp D(IS=1E-15 IBV=1E-13 VJ=0.1)
|
|
.model DzVoutP D(BV=4.3)
|
|
.model DzVoutN D(BV=4.3)
|
|
.model DzSlewP D(BV=10.821)
|
|
.model DzSlewN D(BV=2.842)
|
|
.model DVnoisy D(IS=7.49e-14 KF=9.87e-18)
|
|
.model DINnoisy D(IS=8.58e-21 KF=0.00e0)
|
|
.model DIPnoisy D(IS=8.58e-21 KF=0.00e0)
|
|
*
|
|
.ENDS AMPB
|
|
.ENDS AD8236
|
|
*
|
|
*
|
|
|
|
* AD8634 SPICE Macro-model
|
|
* Function: Amplifier
|
|
*
|
|
* Revision History:
|
|
* Rev. 0.0 (Mar 2014) ADSJ-RM
|
|
* Copyright 2012 by Analog Devices
|
|
*
|
|
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html
|
|
* for License Statement. Use of this model indicates your acceptance
|
|
* of the terms and provisions in the License Statement.
|
|
*
|
|
* modeled:
|
|
* +/-15V (30V) only, not checked at lower voltages
|
|
* modeling based on the typical values stated in the datasheet table
|
|
*
|
|
* Parameters modeled include:VOS , CMRR, PSRR, voltage noise,
|
|
* Vdo, gbw & phase margin, slew rate, CL Zout, Isy, ISC
|
|
*
|
|
* Node assignments
|
|
* non-inverting input
|
|
* | inverting input
|
|
* | | positive supply
|
|
* | | | negative supply
|
|
* | | | | output
|
|
* | | | | |
|
|
.SUBCKT AD8634 1 2 99 50 45
|
|
|
|
|
|
* INPUT STAGE
|
|
*
|
|
Q1 5 11 301 QIN 1; 301
|
|
Q2 6 2 302 QIN 1; 302
|
|
Cx1 5 6 7.0E-12
|
|
Q3 7 11 303 QIP 1; 303
|
|
Q4 8 2 304 QIP 1; 304
|
|
Cx2 7 8 7.0E-12
|
|
DC1 2 11 DC
|
|
DC2 11 2 DC
|
|
Q5 4 9 99 QIP 1;
|
|
Q6 9 9 99 QIP 1
|
|
Q7 3 10 50 QIN 1;
|
|
Q8 10 10 50 QIN 1
|
|
R1 99 5 4.5E3
|
|
R2 99 6 4.5E3
|
|
R3 7 50 4.0E3
|
|
R4 8 50 4.0E3
|
|
RE1 301 3 12.0E+1
|
|
RE2 302 3 12.0E+1
|
|
RE3 303 4 12.0E+1
|
|
RE4 304 4 12.0E+1
|
|
IREF 9 10 69E-06
|
|
GREF 9 10 POLY(1) (99,50) 0 2.5E-07
|
|
EOS 1 11 POLY(4) (81,98)(83,98)(22,98)(73,98) -90E-6 1 1 1 1
|
|
IOS 1 2 -10E-09
|
|
CIN 1 2 1.1E-12
|
|
CICM1 1 50 2.4E-12
|
|
CICM2 2 50 2.4E-12
|
|
Dinp1 1 99 DC
|
|
Dinp2 50 1 DC
|
|
Dinn1 2 99 DC
|
|
Dinn2 50 2 DC
|
|
GN1 1 98 POLY(1) (1,50) 53E-09 -2.15E-9
|
|
GN2 2 98 POLY(1) (2,50) 56E-09 -2.11E-9
|
|
*
|
|
|
|
G101 98 211 POLY(2) (5,6) (7,8) 0 5.3E-04 5.3E-04
|
|
R101 211 98 1.0E6
|
|
*
|
|
E201 311 98 POLY(1) (211,98)0 2.0E+0
|
|
R202 311 321 1.8E+3;
|
|
C202 311 321 8E-16
|
|
R203 321 98 1.8E+3
|
|
*
|
|
E3 252 98 (321 98) 2E-0
|
|
R31 252 253 1.0E+3
|
|
C31 253 252 9E-11; -12
|
|
R32 253 98 1.0E+3
|
|
*
|
|
* GAIN STAGE
|
|
*
|
|
G2 98 251 (253, 98) 1.0E-06
|
|
R5 251 98 8.2E5
|
|
RF 251 250 75.0E+00
|
|
CF 245 250 40.5E-11
|
|
EF (245 98) (45,98) 1
|
|
D3 251 451 DX
|
|
D4 452 251 DX
|
|
V1 451 98 -0.038 ;
|
|
V2 452 98 -0.29
|
|
*
|
|
* CMRR
|
|
*
|
|
ECM 72 98 POLY(2) (1,98) (2,98) 0 3.42E-03 3.42E-03
|
|
RCM1 72 73 3.061E+01
|
|
RCM2 73 98 7.958E-03
|
|
CCM1 72 73 1.0E-6
|
|
*
|
|
* PSRR
|
|
*
|
|
EPSY 21 98 POLY(1) (99,50) -197.534E+00 6.584E-00
|
|
RPS1 21 22 5.341E+03
|
|
RPS2 22 98 7.958E-04
|
|
CPS1 21 22 1.000E-06
|
|
*
|
|
* VOLTAGE NOISE
|
|
*
|
|
VN1 80 98 0
|
|
RN1 80 98 43.5E-3
|
|
HN 81 98 VN1 5.3
|
|
RN2 81 98 1
|
|
*
|
|
* FLICKER NOISE CORNER
|
|
*
|
|
DFN 82 98 DNOISE 1000
|
|
IFN 98 82 DC 1E-03
|
|
DFN2 182 98 DNOISE
|
|
IFN2 98 182 DC 1E-06
|
|
GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-04
|
|
RFN 83 98 1
|
|
*
|
|
D60 60 0 DN1 1000
|
|
I60 0 60 1M
|
|
D61 61 0 DN4
|
|
I61 0 61 1U
|
|
D62 62 0 DN3
|
|
I62 0 62 1U
|
|
D63 63 0 DN2
|
|
I63 0 63 1U
|
|
G60 3 50 61 60 .007
|
|
G61 2 50 61 60 .008
|
|
G62 3 2 62 60 .000092
|
|
*
|
|
* INTERNAL VOLTAGE REFERENCE
|
|
*
|
|
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
|
|
GSY 99 50 POLY(1) (99,50) 403E-6 6.036E-6
|
|
*
|
|
* OUTPUT STAGE
|
|
*
|
|
Q33 450 41 99 POUT
|
|
Cco1 450 41 2.5E-12
|
|
RB1 40 41 1.5E3
|
|
EB1 99 40 POLY(1) (98,251) 7.535E-01 1;
|
|
Q34 450 43 50 NOUT
|
|
Cco2 450 43 5E-12
|
|
RB2 42 43 2.0E3
|
|
EB2 42 50 POLY(1) (251,98) 7.520E-01 1;
|
|
Lout 45 450 1E-09
|
|
*
|
|
* MODELS
|
|
*
|
|
.MODEL DC D(IS=1E-14,CJO=1E-15)
|
|
.MODEL DX D(IS=1E-14,CJO=1E-15)
|
|
.MODEL DY D(IS=1E-16,RS=0.1)
|
|
.MODEL DIN1 D(RS=5.358 KF=56E-15 AF=1)
|
|
.MODEL DIN2 D(RS=5.358 KF=56E-15 AF=1)
|
|
.MODEL DN1 D IS=1E-16
|
|
.MODEL DN2 D IS=1E-16 AF=1 KF=1.05E-17
|
|
.MODEL DN3 D IS=1E-16 AF=1 KF=2.8E-17
|
|
.MODEL DN4 D IS=1E-16 AF=1 KF=4.5E-17
|
|
|
|
.MODEL DNOISE D(IS=1E-16,RS=1E-3,KF=1.14E-11)
|
|
.MODEL QIN NPN(BF=130 VA=200 IS=0.5E-16)
|
|
.MODEL QIP PNP(BF=80 VA=140 IS=0.5E-16)
|
|
.MODEL NOUT NPN(BF=140 VA=350 IS=0.5E-16 BR=8.4 VAR=20 RC=4.0E1)
|
|
.MODEL POUT PNP(BF=80 VA=130 IS=0.5E-16 BR=5 VAR=20 RC=6.0E1)
|
|
*
|
|
.ENDS AD8634
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|
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