jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
89 lines
2.7 KiB
VHDL
89 lines
2.7 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: ir-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:56:39 $
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--
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--------------------------------------------------------------------------
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--
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-- Behavioural architecture of instruction register.
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--
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use work.dlx_instr.all;
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architecture behaviour of ir is
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begin
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reg: process (d, latch_en, immed_sel1, immed_sel2,
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immed_unsigned1, immed_unsigned2, immed_en1, immed_en2)
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variable latched_instr : dlx_word;
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use work.bv_arithmetic.bv_zext, work.bv_arithmetic.bv_sext;
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begin
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if latch_en = '1' then
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latched_instr := d;
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ir_out <= latched_instr after Tpd;
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end if;
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--
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if immed_en1 = '1' then
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if immed_sel1 = immed_size_16 then
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if immed_unsigned1 = '1' then
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immed_q1 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
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else
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immed_q1 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
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end if;
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else -- immed_sel1 = immed_size_26
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if immed_unsigned1 = '1' then
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immed_q1 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
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else
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immed_q1 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
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end if;
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end if;
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else
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immed_q1 <= null after Tpd;
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end if;
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--
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if immed_en2 = '1' then
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if immed_sel2 = immed_size_16 then
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if immed_unsigned2 = '1' then
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immed_q2 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
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else
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immed_q2 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
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end if;
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else -- immed_sel2 = immed_size_26
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if immed_unsigned2 = '1' then
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immed_q2 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
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else
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immed_q2 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
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end if;
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end if;
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else
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immed_q2 <= null after Tpd;
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end if;
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end process reg;
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end behaviour;
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