jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
62 lines
2.6 KiB
VHDL
62 lines
2.6 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: cache.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 21:42:34 $
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--
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--------------------------------------------------------------------------
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--
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-- Entity declaration for cache.
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--
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use work.dlx_types.all,
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work.mem_types.all,
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work.cache_types.all;
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entity cache is
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generic (cache_size : positive; -- in bytes, power of 2
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line_size : positive; -- in bytes, power of 2
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associativity : positive; -- 1 = direct mapped
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write_strategy : strategy_type; -- write_through or copy_back
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Tpd_clk_out : Time; -- clock to output propagation delay
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tag : string := "";
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origin_x, origin_y : real := 0.0);
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port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
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reset : in bit; -- synchronous reset input
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-- connections to CPU
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cpu_enable : in bit; -- starts memory cycle
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cpu_width : in mem_width; -- byte/halfword/word indicator
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cpu_write : in bit; -- selects read or write cycle
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cpu_ready : out bit; -- status from memory system
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cpu_a : in dlx_address; -- address bus output
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cpu_d : inout dlx_word_bus bus; -- bidirectional data bus
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-- connections to memory
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mem_enable : out bit; -- starts memory cycle
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mem_width : out mem_width; -- byte/halfword/word indicator
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mem_write : out bit; -- selects read or write cycle
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mem_burst : out bit; -- tell memory to burst txfer
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mem_ready : in bit; -- status from memory system
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mem_a : out dlx_address; -- address bus output
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mem_d : inout dlx_word_bus bus); -- bidirectional data bus
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end cache;
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