jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
978 lines
28 KiB
VHDL
978 lines
28 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:30:30 08/27/2006
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-- Design Name:
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-- Module Name: ac97_test - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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use work.cpu_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity ac97_test is
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Port (
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sys_rst_n_in : in std_logic;
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sys_clk_in : in std_logic;
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sys_btn : in std_logic_vector(4 downto 0);
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sys_dip : in std_logic_vector(7 downto 0);
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sys_led : out std_logic_vector(8 downto 0);
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sys_rx : in std_logic;
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sys_tx : out std_logic;
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sys_lcd_d : inout std_logic_vector(3 downto 0);
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sys_lcd_e : out std_logic;
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sys_lcd_rs : out std_logic;
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sys_lcd_rw : out std_logic;
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ac97_bit_clk : in STD_LOGIC;
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ac97_sdata_in : in STD_LOGIC;
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ac97_reset_n : out STD_LOGIC;
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ac97_sdata_out : out STD_LOGIC;
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ac97_sync : out STD_LOGIC
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);
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end ac97_test;
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architecture Behavioral of ac97_test is
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constant mix_nbits : integer := 18;
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constant nco_nbits_wave : integer := 18;
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constant nco_nbits_phase : integer := 16;
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constant fir_bp_nbits : integer := 18;
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constant fir_lp_nbits : integer := 18;
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constant f : REAL := 1.0E3;
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constant df : REAL := 100.0;
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constant fa : REAL := 48.0E3;
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constant nco_freq_word : integer := integer(f/fa*2.0**nco_nbits_phase);
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constant nco_freq_inc : integer := integer(df/fa*2.0**nco_nbits_phase);
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type stereo_t is (left, right);
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type pcm_data_t is array (stereo_t) of signed(17 downto 0);
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type stereo_bits_t is array (stereo_t) of std_logic;
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------------------------------------------------------------------
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COMPONENT singleshot
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GENERIC (mode : integer);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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input : IN std_logic;
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output : OUT std_logic
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);
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END COMPONENT;
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COMPONENT ac_io
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Port (
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rst : in std_logic;
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clk : in std_logic;
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ready : out std_logic;
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sync_strobe : out unsigned(0 to 2);
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slot_valid : out unsigned(0 to 12);
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stat_addr : out unsigned (19 downto 0);
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stat_data : out unsigned (19 downto 0);
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rx_pcm_addr : in unsigned (3 downto 0);
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rx_pcm_data : out unsigned (19 downto 0);
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cmd_addr : in unsigned(19 downto 0);
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cmd_data : in unsigned(19 downto 0);
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cmd_we : in std_logic;
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tx_pcm_addr : in unsigned(3 downto 0);
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tx_pcm_data : in unsigned(19 downto 0);
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tx_pcm_we : in std_logic;
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ac_sdata_in : in std_logic;
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ac_bit_clk : in std_logic;
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ac_reset_n : out std_logic;
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ac_sdata_out : out std_logic;
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ac_ssync : out std_logic
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);
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END COMPONENT;
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SIGNAL sync_strobe : unsigned(0 to 2);
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SIGNAL slot_valid : unsigned(0 to 12);
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SIGNAL cmd_we : std_logic;
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SIGNAL cmd_addr : unsigned(19 downto 0);
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SIGNAL cmd_data : unsigned(19 downto 0);
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SIGNAL stat_addr : unsigned(19 downto 0);
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SIGNAL stat_data : unsigned(19 downto 0);
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SIGNAL tx_pcm_addr : unsigned(3 downto 0);
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SIGNAL tx_pcm_data : unsigned(19 downto 0);
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SIGNAL rx_pcm_addr : unsigned(3 downto 0);
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SIGNAL tx_pcm_we : std_logic;
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SIGNAL rx_pcm_data : unsigned(19 downto 0);
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COMPONENT syn_nco
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PORT(
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rst : in std_logic;
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clk : in std_logic;
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pacc_clr : in std_logic;
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pacc_inc : in std_logic;
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freq_in : in unsigned(nco_nbits_phase-1 downto 0);
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freq_load : in std_logic;
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phase_in : in unsigned(nco_nbits_phase-1 downto 0);
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phase_load : in std_logic;
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phase_out : out unsigned(nco_nbits_phase-1 downto 0);
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wave_out_i : out signed(nco_nbits_wave-1 downto 0);
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wave_out_q : out signed(nco_nbits_wave-1 downto 0);
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out_valid : out std_logic
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);
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END COMPONENT;
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SIGNAL nco_pacc_clr : std_logic;
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SIGNAL nco_pacc_inc : std_logic;
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SIGNAL nco_freq_in : unsigned(nco_nbits_phase-1 downto 0);
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SIGNAL nco_freq_load : std_logic;
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SIGNAL nco_phase_in : unsigned(nco_nbits_phase-1 downto 0);
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SIGNAL nco_phase_load : std_logic;
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SIGNAL nco_phase_out : unsigned(nco_nbits_phase-1 downto 0);
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signal pcm_nco_data : pcm_data_t;
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SIGNAL nco_out_valid : std_logic;
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COMPONENT cpu_embedded
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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int_in : in STD_LOGIC;
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int_ack : out STD_LOGIC;
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xmem_we : out STD_LOGIC;
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xmem_re : out STD_LOGIC;
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xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
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io_sel : out STD_LOGIC
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);
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END COMPONENT;
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signal cpu_ce : std_logic;
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signal cpu_int_in : std_logic;
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signal cpu_int_ack : std_logic;
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signal cpu_din : dmem_data_t;
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signal cpu_dout : dmem_data_t;
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signal cpu_addr : dmem_addr_t;
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signal cpu_we : std_logic;
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signal cpu_re : std_logic;
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signal cpu_io_sel : std_logic;
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COMPONENT xrom
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in dmem_addr_t;
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dout : out dmem_data_t
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);
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END COMPONENT;
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signal xrom_data : dmem_data_t;
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COMPONENT syn_fir_bandpass
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PORT(
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rst : in std_logic;
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clk : in std_logic;
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ready_i : out std_logic;
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x_valid_i : in std_logic;
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x_din_i : in signed(fir_bp_nbits-1 downto 0);
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y_valid_i : out std_logic;
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y_dout_i : out signed(fir_bp_nbits-1 downto 0);
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ready_q : out std_logic;
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x_valid_q : in std_logic;
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x_din_q : in signed(fir_bp_nbits-1 downto 0);
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y_valid_q : out std_logic;
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y_dout_q : out signed(fir_bp_nbits-1 downto 0)
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);
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END COMPONENT;
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signal fir_bp_ready : stereo_bits_t;
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signal fir_bp_din_we : stereo_bits_t;
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signal fir_bp_dout_valid : stereo_bits_t;
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signal fir_bp_din : pcm_data_t;
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signal fir_bp_dout : pcm_data_t;
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COMPONENT syn_fir_lowpass
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PORT(
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rst : in std_logic;
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clk : in std_logic;
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ready_i : out std_logic;
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x_valid_i : in std_logic;
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x_din_i : in signed(fir_lp_nbits-1 downto 0);
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y_valid_i : out std_logic;
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y_dout_i : out signed(fir_lp_nbits-1 downto 0);
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ready_q : out std_logic;
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x_valid_q : in std_logic;
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x_din_q : in signed(fir_lp_nbits-1 downto 0);
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y_valid_q : out std_logic;
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y_dout_q : out signed(fir_lp_nbits-1 downto 0)
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);
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END COMPONENT;
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signal fir_lp_ready : stereo_bits_t;
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signal fir_lp_din_we : stereo_bits_t;
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signal fir_lp_dout_valid : stereo_bits_t;
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signal fir_lp_din : pcm_data_t;
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signal fir_lp_dout : pcm_data_t;
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COMPONENT mix_cpx
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GENERIC
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(
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nbits_in : integer;
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nbits_in_frac : integer;
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nbits_out : integer;
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nbits_out_frac : integer;
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nbits_scale_z : integer;
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has_in_reg : boolean;
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has_pipe_reg : boolean;
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has_out_reg : boolean;
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rounding : boolean;
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saturating : boolean
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);
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PORT
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(
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srst : in std_logic;
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clk : in std_logic;
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in_valid : in std_logic;
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x_re_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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x_im_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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y_re_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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y_im_in : in sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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out_valid : out std_logic;
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z_re_out : out sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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z_im_out : out sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low)
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);
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END COMPONENT;
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constant mix_nbits_scale_z : integer := 1;
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signal mix_x_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_x_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_y_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_y_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_z_re : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_z_im : sfixed(sproto(mix_nbits, mix_nbits)'high downto sproto(mix_nbits, mix_nbits)'low);
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signal mix_in_valid : std_logic;
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signal mix_out_valid : std_logic;
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COMPONENT lcd_port
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PORT (
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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lcd_d : inout std_logic_vector(3 downto 0);
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lcd_e : out std_logic;
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lcd_rs : out std_logic;
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lcd_rw : out std_logic
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);
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END COMPONENT;
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signal cpu_lcd_in_reg, cpu_lcd_out_reg : unsigned(DMEM_DATA_WIDTH-1 downto 0);
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signal cpu_lcd_we : std_logic;
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------------------------------------------------------------------
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-- X"1F400", -- W: DAC rate 8000Hz
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-- X"AC440", -- W: DAC rate 44100Hz
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------------------------------------------------------------------
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type state_t is (st_reset, st_pcm_in, st_pcm_in3, st_pcm_in4, st_pcm_out, st_pcm_out3, st_pcm_out4);
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signal rst, clk : std_logic;
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signal acio_ready : std_logic;
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signal nco_freq_set : unsigned(nco_nbits_phase-1 downto 0);
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signal pcm_rom_data : signed(19 downto 0);
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signal pcm_rom_addr : unsigned(9 downto 0);
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signal pcm_active, cmd_active : std_logic;
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signal state, nextstate : state_t;
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signal ac_reset_n : std_logic;
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signal ac_rst : std_logic;
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signal ac_ssync : std_logic;
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signal pcm_request, pcm_request_set, pcm_request_ack : std_logic;
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signal started_up : std_logic := '1';
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signal cpu_freq, cpu_cmd_addr, cpu_cmd_data, cpu_stat_addr, cpu_stat_data : unsigned(15 downto 0);
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signal cpu_mix_dc_adj_left, cpu_mix_dc_adj_right, cpu_pcmin_dc_adj_left, cpu_pcmin_dc_adj_right : unsigned(15 downto 0);
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subtype low is unsigned(7 downto 0);
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subtype high is unsigned(15 downto 8);
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signal pcm_in_data : pcm_data_t;
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signal pcm_out_data : pcm_data_t;
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signal pcm_in_data_we, pcm_in_valid : stereo_bits_t;
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type pcmout_mode_t is (PCMOUT_TONE, PCMOUT_LOOPTHROUGH, PCMOUT_FILTERED, PCMOUT_MIXER, PCMOUT_FM, PCMOUT_BASEBAND);
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signal pcmout_mode : pcmout_mode_t;
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signal pcm_table_data : unsigned(19 downto 0);
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signal cpu_cmd_access, cpu_freq_access, cpu_cmd_ready, cpu_stat_ready : std_logic;
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signal cpu_led_reg, cpu_btn_reg, cpu_dip_reg, cpu_pcmmode_reg : unsigned(DMEM_DATA_WIDTH-1 downto 0);
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signal cpu_cmd_we, cmd_access_is_fsm : std_logic;
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------------------------------------------------------------------
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function GetRequest(slot1 : unsigned) return unsigned is
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variable res : unsigned(3 to 12);
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begin
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res := (others => '0');
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for i in res'range loop
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res(i) := not slot1(14-i);
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end loop;
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return res;
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end GetRequest;
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begin
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------------------------------------------------------------------
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cmd_data <= (cpu_cmd_data & "0000");
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cmd_addr <= (cpu_cmd_addr & "0000");
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ac_rst <= not ac_reset_n;
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ac97_reset_n <= ac_reset_n;
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ac97_sync <= ac_ssync;
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sys_tx <= sys_rx;
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cpu_ce <= '1';
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clk <= sys_clk_in;
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rst <= not (started_up and sys_rst_n_in);
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-- rst <= not (sys_rst_n_in);
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cpu_int_in <= sync_strobe(0);
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fir_bp_din_we(left) <= pcm_in_valid(left) and fir_bp_ready(left);
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fir_bp_din_we(right) <= pcm_in_valid(right) and fir_bp_ready(right);
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fir_bp_din(left to right) <= pcm_in_data(left to right);
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fir_lp_din_we(left) <= mix_out_valid and fir_lp_ready(left);
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fir_lp_din_we(right) <= mix_out_valid and fir_lp_ready(right);
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fir_lp_din(left) <= to_signed(mix_z_re);
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fir_lp_din(right) <= to_signed(mix_z_im);
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------------------------------------------------------------------
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proc_led_btn:
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process (rst, clk)
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begin
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if rising_edge(clk) then
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cpu_btn_reg <= "000" & unsigned(sys_btn);
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cpu_dip_reg <= unsigned(sys_dip);
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if rst = '1' then
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sys_led <= (others => '0');
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else
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sys_led(7 downto 0) <= STD_LOGIC_VECTOR(cpu_led_reg);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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host_din : process (acio_ready, sync_strobe, slot_valid, stat_addr, state, pcm_request, pcm_out_data)
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variable request : unsigned(3 to 12);
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variable rx_frame_valid : std_logic;
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variable sync_frame, sync_status, sync_tx : std_logic;
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begin
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request := GetRequest(stat_addr);
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rx_frame_valid := slot_valid(0);
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sync_frame := sync_strobe(0);
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sync_status := sync_strobe(1);
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sync_tx := sync_strobe(2);
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tx_pcm_we <= '0';
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tx_pcm_addr <= to_unsigned(3, tx_pcm_addr'length);
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tx_pcm_data <= to_unsigned(0, tx_pcm_data'length);
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rx_pcm_addr <= to_unsigned(3, rx_pcm_addr'length);
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nextstate <= state;
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pcm_active <= '0';
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cmd_active <= '0';
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pcm_request_set <= '0';
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pcm_request_ack <= '0';
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pcm_in_data_we <= (others => '0');
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nco_pacc_inc <= '0';
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nco_pacc_clr <= '0';
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nco_phase_in <= (others => '0');
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nco_phase_load <= '0';
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case state is
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when st_reset =>
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if rx_frame_valid = '1' and sync_status = '1' and acio_ready = '1' then
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nextstate <= st_pcm_in;
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end if;
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when st_pcm_in =>
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if rx_frame_valid = '1' and sync_frame = '1' then
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nextstate <= st_pcm_in3;
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end if;
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when st_pcm_in3 =>
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nextstate <= st_pcm_in4;
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rx_pcm_addr <= to_unsigned(3, rx_pcm_addr'length);
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if slot_valid(3) = '1' then
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pcm_in_data_we(left) <= '1';
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end if;
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when st_pcm_in4 =>
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nextstate <= st_pcm_out;
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rx_pcm_addr <= to_unsigned(4, rx_pcm_addr'length);
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if slot_valid(4) = '1' then
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pcm_in_data_we(right) <= '1';
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end if;
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when st_pcm_out =>
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pcm_active <= '1';
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if rx_frame_valid = '1' and sync_status = '1' then
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if request(3) = '1' and request(4) = '1' then
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pcm_request_set <= '1';
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nco_pacc_inc <= '1';
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end if;
|
|
end if;
|
|
if pcm_request = '1' and sync_tx = '1' then
|
|
nextstate <= st_pcm_out3;
|
|
end if;
|
|
|
|
when st_pcm_out3 =>
|
|
tx_pcm_data <= unsigned(pcm_out_data(left)) & "00";
|
|
pcm_active <= '1';
|
|
tx_pcm_addr <= to_unsigned(3, tx_pcm_addr'length);
|
|
tx_pcm_we <= '1';
|
|
pcm_request_ack <= '1';
|
|
nextstate <= st_pcm_out4;
|
|
|
|
when st_pcm_out4 =>
|
|
tx_pcm_data <= unsigned(pcm_out_data(right)) & "00";
|
|
pcm_active <= '1';
|
|
tx_pcm_addr <= to_unsigned(4, tx_pcm_addr'length);
|
|
tx_pcm_we <= '1';
|
|
nextstate <= st_pcm_in;
|
|
|
|
when others =>
|
|
nextstate <= st_reset;
|
|
|
|
end case;
|
|
|
|
end process;
|
|
|
|
proc_fsm_next:
|
|
process (rst, clk, nextstate)
|
|
begin
|
|
if rst = '1' then
|
|
state <= st_reset;
|
|
elsif rising_edge(clk) then
|
|
state <= nextstate;
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_pcm_in
|
|
-------------------------------------------------------------
|
|
proc_pcm_in:
|
|
process (rst, clk, pcm_in_data_we, rx_pcm_data)
|
|
variable dc_adj : pcm_data_t;
|
|
begin
|
|
dc_adj(left) := resize(signed(cpu_pcmin_dc_adj_left), dc_adj(left)'length);
|
|
dc_adj(right) := resize(signed(cpu_pcmin_dc_adj_right), dc_adj(right)'length);
|
|
|
|
if rst = '1' then
|
|
for i in pcm_in_data'range loop
|
|
dc_adj(i) := (others => '0');
|
|
pcm_in_data(i) <= (others => '0');
|
|
pcm_in_valid(i) <= '0';
|
|
end loop;
|
|
elsif rising_edge(clk) then
|
|
for i in pcm_in_data'range loop
|
|
pcm_in_valid(i) <= '0';
|
|
end loop;
|
|
for i in pcm_in_data'range loop
|
|
if pcm_in_data_we(i) = '1' then
|
|
pcm_in_valid(i) <= '1';
|
|
pcm_in_data(i) <= dc_adj(i) + signed(rx_pcm_data(19 downto 2));
|
|
end if;
|
|
end loop;
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_mix_input
|
|
-------------------------------------------------------------
|
|
proc_mix_input:
|
|
process (rst, clk)
|
|
begin
|
|
|
|
if rst = '1' then
|
|
mix_in_valid <= '0';
|
|
mix_x_re <= to_sfixed(0.0, mix_x_re);
|
|
mix_x_im <= to_sfixed(0.0, mix_x_im);
|
|
elsif rising_edge(clk) then
|
|
mix_in_valid <= '0';
|
|
if fir_bp_dout_valid(right) = '1' then
|
|
mix_in_valid <= '1';
|
|
mix_x_re <= sfixed(signed(cpu_mix_dc_adj_left) + fir_bp_dout(left));
|
|
mix_x_im <= sfixed(signed(cpu_mix_dc_adj_right) + fir_bp_dout(right));
|
|
end if;
|
|
mix_y_re <= sfixed(pcm_nco_data(left));
|
|
mix_y_im <= sfixed(pcm_nco_data(right));
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_pcmout_mode_mapper
|
|
-------------------------------------------------------------
|
|
proc_pcmout_mode_mapper:
|
|
process (cpu_pcmmode_reg)
|
|
begin
|
|
case cpu_pcmmode_reg is
|
|
when X"00" =>
|
|
pcmout_mode <= PCMOUT_LOOPTHROUGH;
|
|
when X"01" =>
|
|
pcmout_mode <= PCMOUT_FILTERED;
|
|
when X"02" =>
|
|
pcmout_mode <= PCMOUT_TONE;
|
|
when X"03" =>
|
|
pcmout_mode <= PCMOUT_MIXER;
|
|
when X"04" =>
|
|
pcmout_mode <= PCMOUT_FM;
|
|
when X"05" =>
|
|
pcmout_mode <= PCMOUT_BASEBAND;
|
|
when others =>
|
|
pcmout_mode <= PCMOUT_LOOPTHROUGH;
|
|
end case;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_pcm_out_mux
|
|
-------------------------------------------------------------
|
|
proc_pcm_out_mux:
|
|
process (clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
case pcmout_mode is
|
|
when PCMOUT_TONE | PCMOUT_FM =>
|
|
pcm_out_data(left to right) <= pcm_nco_data(left to right);
|
|
when PCMOUT_LOOPTHROUGH =>
|
|
pcm_out_data(left to right) <= pcm_in_data(left to right);
|
|
when PCMOUT_FILTERED =>
|
|
pcm_out_data(left to right) <= fir_bp_dout(left to right);
|
|
when PCMOUT_MIXER =>
|
|
pcm_out_data(left) <= to_signed(mix_z_re);
|
|
pcm_out_data(right) <= to_signed(mix_z_im);
|
|
when PCMOUT_BASEBAND =>
|
|
pcm_out_data(left to right) <= fir_lp_dout(left to right);
|
|
when others =>
|
|
pcm_out_data(left to right) <= pcm_nco_data(left to right);
|
|
end case;
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_freq_mod
|
|
-------------------------------------------------------------
|
|
proc_freq_mod:
|
|
process (clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if rst = '1' then
|
|
nco_freq_set <= to_unsigned(nco_freq_word, nco_nbits_phase);
|
|
elsif cpu_freq_access = '1' then
|
|
nco_freq_set <= cpu_freq;
|
|
end if;
|
|
if pcmout_mode = PCMOUT_FM then
|
|
nco_freq_in <= unsigned(fir_bp_dout(left)(nco_freq_in'left downto 2) + signed(nco_freq_set));
|
|
else
|
|
nco_freq_in <= nco_freq_set;
|
|
end if;
|
|
nco_freq_load <= fir_bp_dout_valid(left);
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_cpu_flags
|
|
-------------------------------------------------------------
|
|
proc_cpu_stat_reg_control:
|
|
process (clk, sync_strobe, slot_valid)
|
|
variable rx_frame_valid : std_logic;
|
|
variable sync_frame, sync_status, sync_tx : std_logic;
|
|
begin
|
|
rx_frame_valid := slot_valid(0);
|
|
sync_frame := sync_strobe(0);
|
|
sync_status := sync_strobe(1);
|
|
sync_tx := sync_strobe(2);
|
|
|
|
if rising_edge(clk) then
|
|
if rst = '1' then
|
|
cpu_cmd_ready <= '0';
|
|
cpu_stat_ready <= '0';
|
|
cpu_stat_addr <= (others => '0');
|
|
cpu_stat_data <= (others => '0');
|
|
else
|
|
cpu_cmd_we <= '0';
|
|
if cpu_cmd_access = '1' then
|
|
cpu_cmd_ready <= '0';
|
|
cpu_stat_ready <= '0';
|
|
end if;
|
|
|
|
if cpu_cmd_ready = '0' then
|
|
if sync_tx = '1' and rx_frame_valid = '1' then
|
|
cpu_cmd_we <= '1';
|
|
cpu_cmd_ready <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
if sync_status = '1' and slot_valid(0 to 2) = "111" then
|
|
cpu_stat_ready <= '1';
|
|
cpu_stat_addr <= stat_addr(19 downto 4);
|
|
cpu_stat_data <= stat_data(19 downto 4);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_cpu_dout_reg
|
|
-------------------------------------------------------------
|
|
proc_cpu_dout_reg:
|
|
process (clk)
|
|
variable addr : dmem_addr_t;
|
|
begin
|
|
if rising_edge(clk) then
|
|
if rst = '1' then
|
|
cpu_led_reg <= (others => '0');
|
|
cpu_pcmmode_reg <= (others => '0');
|
|
cpu_freq <= (others => '0');
|
|
cpu_cmd_addr <= (others => '0');
|
|
cpu_cmd_data <= (others => '0');
|
|
cpu_lcd_out_reg <= (others => '0');
|
|
cpu_mix_dc_adj_left <= (others => '0');
|
|
cpu_mix_dc_adj_right <= (others => '0');
|
|
cpu_pcmin_dc_adj_left <= (others => '0');
|
|
cpu_pcmin_dc_adj_right <= (others => '0');
|
|
else
|
|
addr := cpu_addr;
|
|
cpu_cmd_access <= '0';
|
|
cpu_freq_access <= '0';
|
|
cpu_lcd_we <= '0';
|
|
if cpu_we = '1' and cpu_io_sel = '1' then
|
|
case addr is
|
|
when X"00" =>
|
|
cpu_led_reg <= cpu_dout;
|
|
when X"01" =>
|
|
cpu_pcmmode_reg <= cpu_dout;
|
|
when X"02" =>
|
|
cpu_freq_access <= '1';
|
|
cpu_freq(low'range) <= cpu_dout;
|
|
when X"03" =>
|
|
cpu_freq(high'range) <= cpu_dout;
|
|
when X"04" =>
|
|
cpu_cmd_addr(low'range) <= cpu_dout;
|
|
when X"05" =>
|
|
cpu_cmd_addr(high'range) <= cpu_dout;
|
|
when X"06" =>
|
|
cpu_cmd_access <= '1';
|
|
cpu_cmd_data(low'range) <= cpu_dout;
|
|
when X"07" =>
|
|
cpu_cmd_data(high'range) <= cpu_dout;
|
|
when X"08" =>
|
|
cpu_lcd_we <= '1';
|
|
cpu_lcd_out_reg <= cpu_dout;
|
|
when X"09" =>
|
|
cpu_mix_dc_adj_left(low'range) <= cpu_dout;
|
|
when X"0A" =>
|
|
cpu_mix_dc_adj_left(high'range) <= cpu_dout;
|
|
when X"0B" =>
|
|
cpu_mix_dc_adj_right(low'range) <= cpu_dout;
|
|
when X"0C" =>
|
|
cpu_mix_dc_adj_right(high'range) <= cpu_dout;
|
|
when X"0D" =>
|
|
cpu_pcmin_dc_adj_left(low'range) <= cpu_dout;
|
|
when X"0E" =>
|
|
cpu_pcmin_dc_adj_left(high'range) <= cpu_dout;
|
|
when X"0F" =>
|
|
cpu_pcmin_dc_adj_right(low'range) <= cpu_dout;
|
|
when X"10" =>
|
|
cpu_pcmin_dc_adj_right(high'range) <= cpu_dout;
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------
|
|
-- proc_cpu_din_reg
|
|
-------------------------------------------------------------
|
|
proc_cpu_din_reg:
|
|
process (clk, cpu_io_sel, xrom_data)
|
|
variable mix_xre, mix_xim : signed (mix_nbits-1 downto 0);
|
|
variable mix_yre, mix_yim : signed (mix_nbits-1 downto 0);
|
|
variable addr : dmem_addr_t;
|
|
begin
|
|
|
|
mix_xre := to_signed(mix_x_re);
|
|
mix_xim := to_signed(mix_x_im);
|
|
mix_yre := to_signed(mix_y_re);
|
|
mix_yim := to_signed(mix_y_im);
|
|
|
|
if rising_edge(clk) then
|
|
addr := cpu_addr;
|
|
end if;
|
|
|
|
if cpu_io_sel = '0' then
|
|
cpu_din <= xrom_data;
|
|
else
|
|
case addr is
|
|
when X"00" =>
|
|
cpu_din <= cpu_led_reg;
|
|
when X"01" =>
|
|
cpu_din <= cpu_pcmmode_reg;
|
|
when X"02" =>
|
|
cpu_din <= cpu_freq(low'range);
|
|
when X"03" =>
|
|
cpu_din <= cpu_freq(high'range);
|
|
when X"04" =>
|
|
cpu_din <= cpu_stat_addr(low'range);
|
|
when X"05" =>
|
|
cpu_din <= cpu_stat_addr(high'range);
|
|
when X"06" =>
|
|
cpu_din <= cpu_stat_data(low'range);
|
|
when X"07" =>
|
|
cpu_din <= cpu_stat_data(high'range);
|
|
when X"08" =>
|
|
cpu_din <= cpu_lcd_in_reg;
|
|
when X"09" =>
|
|
cpu_din <= cpu_mix_dc_adj_left(low'range);
|
|
when X"0A" =>
|
|
cpu_din <= cpu_mix_dc_adj_left(high'range);
|
|
when X"0B" =>
|
|
cpu_din <= cpu_mix_dc_adj_right(low'range);
|
|
when X"0C" =>
|
|
cpu_din <= cpu_mix_dc_adj_right(high'range);
|
|
when X"0D" =>
|
|
cpu_din <= cpu_pcmin_dc_adj_left(low'range);
|
|
when X"0E" =>
|
|
cpu_din <= cpu_pcmin_dc_adj_left(high'range);
|
|
when X"0F" =>
|
|
cpu_din <= cpu_pcmin_dc_adj_right(low'range);
|
|
when X"10" =>
|
|
cpu_din <= cpu_pcmin_dc_adj_right(high'range);
|
|
when X"80" =>
|
|
cpu_din <= cpu_btn_reg;
|
|
when X"81" =>
|
|
cpu_din <= cpu_dip_reg;
|
|
when X"82" =>
|
|
cpu_din <= dmem_data_t(pcm_in_data(left)(low'range));
|
|
when X"83" =>
|
|
cpu_din <= dmem_data_t(pcm_in_data(left)(high'range));
|
|
when X"84" =>
|
|
cpu_din <= dmem_data_t(pcm_in_data(right)(low'range));
|
|
when X"85" =>
|
|
cpu_din <= dmem_data_t(pcm_in_data(right)(high'range));
|
|
when X"86" =>
|
|
cpu_din <= dmem_data_t(mix_xre(low'range));
|
|
when X"87" =>
|
|
cpu_din <= dmem_data_t(mix_xre(high'range));
|
|
when X"88" =>
|
|
cpu_din <= dmem_data_t(mix_xim(low'range));
|
|
when X"89" =>
|
|
cpu_din <= dmem_data_t(mix_xim(high'range));
|
|
when X"8A" =>
|
|
cpu_din <= dmem_data_t(mix_yre(low'range));
|
|
when X"8B" =>
|
|
cpu_din <= dmem_data_t(mix_yre(high'range));
|
|
when X"8C" =>
|
|
cpu_din <= dmem_data_t(mix_yim(low'range));
|
|
when X"8D" =>
|
|
cpu_din <= dmem_data_t(mix_yim(high'range));
|
|
when X"A0" =>
|
|
cpu_din <= "0000" & (fir_bp_ready(left) and fir_bp_ready(right)) & cpu_stat_ready & cpu_cmd_ready & (pcm_active and acio_ready and slot_valid(0));
|
|
when others =>
|
|
if addr(0) = '0' then
|
|
cpu_din <= X"EF";
|
|
else
|
|
cpu_din <= X"BE";
|
|
end if;
|
|
end case;
|
|
end if;
|
|
|
|
end process;
|
|
-------------------------------------------------------------
|
|
proc_pcm_request:
|
|
process (clk, pcm_request_set, pcm_request_ack)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if pcm_request_ack = '1' or rst = '1' then
|
|
pcm_request <= '0';
|
|
elsif pcm_request_set = '1' then
|
|
pcm_request <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
------------------------------------------------------------------
|
|
-- Instantiate the Unit Under Test (UUT)
|
|
inst_ac_io: ac_io PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
ready => acio_ready,
|
|
sync_strobe => sync_strobe,
|
|
slot_valid => slot_valid,
|
|
stat_addr => stat_addr,
|
|
stat_data => stat_data,
|
|
rx_pcm_addr => rx_pcm_addr,
|
|
rx_pcm_data => rx_pcm_data,
|
|
cmd_addr => cmd_addr,
|
|
cmd_data => cmd_data,
|
|
cmd_we => cpu_cmd_we,
|
|
tx_pcm_addr => tx_pcm_addr,
|
|
tx_pcm_data => tx_pcm_data,
|
|
tx_pcm_we => tx_pcm_we,
|
|
ac_sdata_in => ac97_sdata_in,
|
|
ac_bit_clk => ac97_bit_clk,
|
|
ac_reset_n => ac_reset_n,
|
|
ac_sdata_out => ac97_sdata_out,
|
|
ac_ssync => ac_ssync
|
|
);
|
|
|
|
inst_syn_nco: syn_nco
|
|
PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
pacc_clr => nco_pacc_clr,
|
|
pacc_inc => nco_pacc_inc,
|
|
freq_in => nco_freq_in,
|
|
freq_load => nco_freq_load,
|
|
phase_in => nco_phase_in,
|
|
phase_load => nco_phase_load,
|
|
phase_out => nco_phase_out,
|
|
wave_out_i => pcm_nco_data(left),
|
|
wave_out_q => pcm_nco_data(right),
|
|
out_valid => nco_out_valid
|
|
);
|
|
|
|
inst_cpu_embedded: cpu_embedded
|
|
PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
ce => cpu_ce,
|
|
int_in => cpu_int_in,
|
|
int_ack => cpu_int_ack,
|
|
xmem_we => cpu_we,
|
|
xmem_re => cpu_re,
|
|
xmem_din => cpu_din,
|
|
xmem_dout => cpu_dout,
|
|
xmem_addr => cpu_addr,
|
|
io_sel => cpu_io_sel
|
|
);
|
|
|
|
inst_xrom: xrom
|
|
PORT MAP(
|
|
clk => clk,
|
|
ce => cpu_ce,
|
|
addr => cpu_addr,
|
|
dout => xrom_data
|
|
);
|
|
|
|
inst_syn_fir_bandpass: syn_fir_bandpass
|
|
PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
ready_i => fir_bp_ready(left),
|
|
x_valid_i => fir_bp_din_we(left),
|
|
x_din_i => fir_bp_din(left),
|
|
y_valid_i => fir_bp_dout_valid(left),
|
|
y_dout_i => fir_bp_dout(left),
|
|
ready_q => fir_bp_ready(right),
|
|
x_valid_q => fir_bp_din_we(right),
|
|
x_din_q => fir_bp_din(right),
|
|
y_valid_q => fir_bp_dout_valid(right),
|
|
y_dout_q => fir_bp_dout(right)
|
|
);
|
|
|
|
inst_syn_fir_lowpass: syn_fir_lowpass
|
|
PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
ready_i => fir_lp_ready(left),
|
|
x_valid_i => fir_lp_din_we(left),
|
|
x_din_i => fir_lp_din(left),
|
|
y_valid_i => fir_lp_dout_valid(left),
|
|
y_dout_i => fir_lp_dout(left),
|
|
ready_q => fir_lp_ready(right),
|
|
x_valid_q => fir_lp_din_we(right),
|
|
x_din_q => fir_lp_din(right),
|
|
y_valid_q => fir_lp_dout_valid(right),
|
|
y_dout_q => fir_lp_dout(right)
|
|
);
|
|
|
|
inst_mix_cpx: mix_cpx
|
|
GENERIC MAP
|
|
(
|
|
nbits_in => mix_nbits,
|
|
nbits_in_frac => mix_nbits,
|
|
nbits_out => mix_nbits,
|
|
nbits_out_frac => mix_nbits,
|
|
nbits_scale_z => mix_nbits_scale_z,
|
|
has_in_reg => true,
|
|
has_pipe_reg => true,
|
|
has_out_reg => true,
|
|
rounding => false,
|
|
saturating => false
|
|
)
|
|
PORT MAP
|
|
(
|
|
srst => rst,
|
|
clk => clk,
|
|
in_valid => mix_in_valid,
|
|
x_re_in => mix_x_re,
|
|
x_im_in => mix_x_im,
|
|
y_re_in => mix_y_re,
|
|
y_im_in => mix_y_im,
|
|
out_valid => mix_out_valid,
|
|
z_re_out => mix_z_re,
|
|
z_im_out => mix_z_im
|
|
);
|
|
|
|
inst_lcd_port: lcd_port
|
|
PORT MAP(
|
|
rst => rst,
|
|
clk => clk,
|
|
we => cpu_lcd_we,
|
|
din => cpu_lcd_out_reg,
|
|
dout => cpu_lcd_in_reg,
|
|
lcd_d => sys_lcd_d,
|
|
lcd_e => sys_lcd_e,
|
|
lcd_rs => sys_lcd_rs,
|
|
lcd_rw => sys_lcd_rw
|
|
);
|
|
|
|
------------------------------------------------------------------
|
|
STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4
|
|
port map (
|
|
EOS => started_up, -- End of Startup 1-bit output
|
|
CLK => open, -- Clock input for start-up sequence
|
|
GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name)
|
|
GTS => '0', -- Global 3-state input (GTS cannot be used for the port name)
|
|
USRCCLKO => '0', -- USRCCLKO 1-bit input
|
|
USRCCLKTS => '0', -- USRCCLKTS 1-bit input
|
|
USRDONEO => '0', -- USRDONEO 1-bit input
|
|
USRDONETS => '0' -- USRDONETS 1-bit input
|
|
);
|
|
|
|
------------------------------------------------------------------
|
|
|
|
end Behavioral;
|
|
|