jens
3638a97abf
git-svn-id: http://moon:8086/svn/vhdl/trunk@1341 cc03376c-175c-47c8-b038-4cd826a8556b
97 lines
2.7 KiB
VHDL
97 lines
2.7 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity tb_juart_tx is
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end;
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architecture behave of tb_juart_tx is
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-- Number of user data words for simulation
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal en_16_x_baud : std_logic := '1';
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signal send_character : std_logic := '0';
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signal serial_out : std_logic;
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signal Tx_complete : std_logic;
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signal data_in : unsigned(7 downto 0) := (others => '0');
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begin
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inst_juart_tx : entity work.juart_tx
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PORT MAP
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(
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rst => rst,
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clk => clk,
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en_16_x_baud => en_16_x_baud,
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send_character => send_character,
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Tx_complete => Tx_complete,
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data_in => data_in,
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serial_out => serial_out
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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------------------------------------------------------------------------------------------
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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rst <= '0';
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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data_in <= X"A5";
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wait until rising_edge(clk) and Tx_complete = '1';
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send_character <= '1';
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wait until rising_edge(clk) and Tx_complete = '0';
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send_character <= '0';
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wait until rising_edge(clk) and Tx_complete = '1';
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data_in <= X"AA";
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wait until rising_edge(clk) and Tx_complete = '1';
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send_character <= '1';
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wait until rising_edge(clk) and Tx_complete = '0';
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send_character <= '0';
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data_in <= X"55";
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wait until rising_edge(clk) and Tx_complete = '1';
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send_character <= '1';
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wait until rising_edge(clk) and Tx_complete = '0';
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send_character <= '0';
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wait;
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end process;
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end architecture behave;
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