jens b5e1d45b20 - added test color register base + 0x80 ...

- control signals derived from register file are noe registered for better timing
- mem_offset updated from vga_mem_offset wehn new frame begins
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git-svn-id: http://moon:8086/svn/vhdl/trunk@459 cc03376c-175c-47c8-b038-4cd826a8556b

2009-05-01 19:26:43 +00:00

..

sim

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

src

- added test color register base + 0x80

2009-05-01 19:26:43 +00:00