jens
f585adb8b7
- CRLF git-svn-id: http://moon:8086/svn/vhdl/trunk@1052 cc03376c-175c-47c8-b038-4cd826a8556b
193 lines
6.5 KiB
VHDL
193 lines
6.5 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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ENTITY ssram_port_wb IS
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Generic
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(
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latency : natural := 2; -- clock cycles
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addr_width : natural := 20;
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data_width : natural := 32;
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parity_width : natural := 4
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);
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Port
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(
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-- J-Bus domain
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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-- Sync SRAM domain
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ssram_clk_o : out std_logic;
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ssram_clk_fb : in std_logic;
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ssram_cke_n : out std_logic;
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ssram_ce_n : out std_logic;
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port_bsyi : in std_logic;
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port_bsyo : out std_logic;
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port_a : out unsigned(addr_width-1 downto 0);
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port_di : in unsigned(data_width-1 downto 0);
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port_do : out unsigned(data_width-1 downto 0);
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port_d_drv : out STD_LOGIC;
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port_wr : out STD_LOGIC;
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port_rd : out STD_LOGIC;
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ssram_adv : out std_logic;
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ssram_mode : out std_logic;
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ssram_zz : out std_logic;
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ssram_dp : inout unsigned(parity_width-1 downto 0);
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ssram_bw_n : out unsigned(3 downto 0)
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);
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END ssram_port_wb;
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ARCHITECTURE behavior OF ssram_port_wb IS
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constant topad : time := 3 ns;
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subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0);
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type data_pipe_t is array (latency downto 0) of ssram_d_t;
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signal ssram_clk : std_logic;
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signal dcm_locked : std_logic;
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signal dcm_clk0 : std_logic;
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signal dcm_clk1 : std_logic;
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signal data_en : std_logic;
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signal drive : std_logic;
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signal busy : std_logic;
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signal bsy_pipe : unsigned(latency downto 0);
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signal vld_pipe : unsigned(latency downto 0);
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signal drive_pipe : unsigned(latency downto 0);
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signal data_pipe : data_pipe_t;
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signal ssram_dout : ssram_d_t;
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begin
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SRDY_O <= CYC_I and dcm_locked and not port_bsyi;
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ACK_O <= vld_pipe(vld_pipe'left);
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DAT_O(data_width-1 downto 0) <= port_di;
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data_en <= CYC_I and STB_I and not port_bsyi;
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ssram_dout <= "0000" & DAT_I(data_width-1 downto 0);
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drive <= drive_pipe(drive_pipe'left);
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ssram_clk_o <= ssram_clk after topad;
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ssram_cke_n <= not dcm_locked after topad;
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port_a <= ADDR_I(addr_width-1 downto 0);
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port_do <= data_pipe(data_pipe'left-1)(data_width-1 downto 0);
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port_d_drv <= drive_pipe(drive_pipe'left-1);
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port_wr <= not (WE_I and data_en);
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port_rd <= not (vld_pipe(vld_pipe'left-2) or vld_pipe(vld_pipe'left-1));
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busy <= '1' when bsy_pipe /= (latency downto 0 => '0') else '0';
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port_bsyo <= busy or data_en;
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inst_clock_out : ODDR
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generic map
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(
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DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
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INIT => '0', -- Initial value for Q port ('1' or '0')
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SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
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)
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port map (
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Q => ssram_clk, -- 1-bit DDR output
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C => dcm_clk1, -- 1-bit clock input
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CE => '1', -- 1-bit clock enable input
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D1 => '1', -- 1-bit data input (positive edge)
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D2 => '0', -- 1-bit data input (negative edge)
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R => '0', -- 1-bit reset input
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S => '0' -- 1-bit set input
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);
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ssram_bufg: bufg
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port map
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(
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o => dcm_clk1,
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i => dcm_clk0
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);
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inst_DCM_BASE_0 : DCM_BASE
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
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CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
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DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
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DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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-- an integer from 0 to 15
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DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
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PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
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STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
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port map (
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CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => open, -- 270 degree DCM CLK output
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CLK2X => open, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLK90 => open, -- 90 degree DCM CLK output
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => open, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => dcm_locked, -- DCM LOCK status output
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CLKFB => ssram_clk_fb, -- DCM clock feedback
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CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM)
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RST => RST_I -- DCM asynchronous reset input
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);
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data_valid_pipeline:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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vld_pipe <= (others => '0');
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bsy_pipe <= (others => '0');
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else
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bsy_pipe <= bsy_pipe(bsy_pipe'left-1 downto 0) & (data_en);
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vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I);
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end if;
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end if;
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end process;
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data_out_pipeline:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ssram_ce_n <= '1' after topad;
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ssram_adv <= '0' after topad;
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ssram_mode <= '0' after topad;
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ssram_zz <= '1' after topad;
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drive_pipe <= (others => '0');
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else
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ssram_ce_n <= not data_en after topad;
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ssram_adv <= '0' after topad;
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ssram_mode <= '0' after topad;
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ssram_zz <= '0' after topad;
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ssram_bw_n <= not SEL_I after topad;
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drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I);
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data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout;
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end if;
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end if;
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end process;
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ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad;
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end behavior;
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